SU1310840A1 - Device for determining arithmetic mean value - Google Patents

Abstract

The invention relates to computing and can be used in systems for processing measurement results. The purpose of the invention is to increase the speed. The device allows to increase the speed of calculating the arithmetic mean value by parallelizing the calculations in time. The device contains registers 2,4,5,6,10, elements OR 3.16, trigger 7, generator 8 clock pulses, elements 9,11, 19 delays, block 12 associative memory, adders 14, 15, subtractor 1.7, switch 18, elements And 20, 21, 22, counter 23, threshold element 26. 1 ill., 2 tab. (L 00 00 4

Description

113

The invention relates to computing and can be used in automatic control devices, information processing and in systems of automation of scientific research.

The aim of the invention is to increase speed by comparing the arithmetic mean of the numbers stored in the memory in parallel over time, independent of their number.

The drawing shows a block diagram of the device.

The device contains input 1 for starting shift register 2, element OR 3, shift register 4, register 5, register 6, trigger 7, clock generator 8, delay element 9, register 10, delay element 11, associative memory block 12, bit The codes of block 12, combinational adder 14, adder 15, elements OR 16 whose outputs are connected to the inputs of subtractor 17, switch 18, delay element 19, elements 20–22, counter 23, input 24 of the initial setting of the average arithmetic unit, output 25 of the device, the threshold element 26.

The device works as follows.

Before starting work on the input 24, the code M of the required bit size of the result (the arithmetic average value obtained) is entered into the counter 23.

The trigger signal, input 1, sets register bits 2,5,4,10 to zero, sets trigger 1 and register register 6 in one state, generates 8 clock pulses, and delays unit 1 through the first delay element 9 in the low bit of register 2. The pulse from the generator 8 through the delay element 11 initiates polling of the block 12, at the outputs of which coincidence signals are generated for all words whose low bit is equal to one. The information from the outputs 13 is fed to the inputs of the adder 14, the output of which forms the binary code of the sum of the number of matches. The resulting number is fed to the first input of the adder 15, where it is added to the contents of register 10 shifted by one bit (the signal 08082

 start through the elements OR 3) so that the i-th bit of the register 10 corresponds to the addition of the (1 + 1) -th bit of the second input of the adder 15. The result is entered into the register 10, and the least significant bit of the (n-th) register 10 is entered with a shift to the left by register 4, beginning with the t-th bit.

The pulse generated by the generator 0 of pulses 8, passing through the delay element 19, causes a shift to the left of the contents of register 2 and, having passed through an open single signal from the output of the trigger 7 element AND 21, you are left to shift to the left of the contents of register 4. With the formation of m generator B the next signal, the next call is to block 12 and the device operates in the same way as

20 until the output of the register 2 shift overflow produces a single level signal (corresponding to the 1st polling cycle of block 12, where 1 is the digit number stored in block 12), which sets trigger 7 to zero. The signal from the inverse output of the trigger 7 goes to the elements And 20, 22, allowing the reader 17 to work and the register 4 to shift to the right.

The code of the number stored in register 10 is fed through the elements OR 16 to the input of threshold element 26 and reader 35. If this number is less than the number of K numbers in block 12, then (t + 1) -th bit of register 4 is entered , and in register 5 through the switch 18 is the original number. If this

40 the number is greater than or equal to K, then in (t + H-1) -th bit of register 4 is entered one, and in register 5 through the switch 18 the difference between the number received at the input of subtractor 17 and

45 number K. The operation of the subtractor 17 is synchronized by the clock signal delayed by the delay element 11 through the element 20. This same signal, additionally delayed by the element

50 19 delay, forms at the input of the element AND 22 a signal, which is used to reset the register 10 to zero and write the code to register 5, and also record the signal in (t + 1) -th bit of the register 55, performed simultaneously right shift the contents of the latter. In addition, the pulse from the output of the element 11 delay through the element And 20 is fed to the counter 23,

3

where the unit is subtracted from the contents of the counter 23. Subsequently, each (j-1) -th input (, 3, ..., p-1) of the subtractor 17 receives a signal from the j-ro output of register 5, and on (z- 1) -th input of the subtractor node 17 - signal from the output of the register 4.

The described sequence of operations is repeated until the contents of the counter 23 is equal to zero. In this case, in the shift register 4, the arithmetic average will be formed with an accuracy of M bits, with the highest bit of the average being located on the right.

Example. Let the arithmetic average of the 4-rand numbers written in the cells of block 12 as

Let M 6 be next. Then, the operation of the device prior to trigger switching 7 is illustrated in Table 1.

The operation of the device after switching the control trigger 7 is illustrated in Table 2.

The resulting code 1010.11 corresponds to a decimal number of 10, 75, i.e. arithmetic mean of given numbers.

The device allows to calculate the arithmetic average for the number of cycles (M + 1), independent of the number of numbers K.

Claims (1)

Invention Formula A device for determining the arithmetic average value, comprising a counter, a delay element, the first, second and third AND elements, an OR element, a trigger, a clock generator, the start input of which is connected to the installation input of the trigger and is a 1-start input the device, the direct output of the trigger is connected to the first input of the first element AND, the inverse output of the trigger is connected to the first inputs of the second and third elements AND, the output of the second element AND is connected to the first input of the element OR, characterized in that Vyshen speed, it introduced a block associative memory, three D 404 gistra, two shift registers, combinational adder, adder, subtractor, switch, group of elements OR, second and third elements delays, outputs of the associative memory unit are connected to the inputs of the combinational adder, the bit outputs of which are connected to the bit inputs of the first group of inputs of the adder, the bit outputs of which are connected to the information input of the first register, the i-th bit output of which (i t , 2, ..., p-1, p - the nearest integer number greater than 1O§K, K - the number of cells of the associative memory block) is connected to the i-th bit input of the second group of inputs of the adder and the first input i -ro element OR group, the output of which is connected to the iM information input The group of inputs of the subtractor, with the i-th input of the group of inputs of the threshold element, with the iM information input of the first group of inputs of the switch, the output of the second is connected to the information input of the second register, whose j-bit output (J 2, ..., p-1 ), connected to the second input (jl) -ro of the OR element of the group, the start input of the clock pulse generator is connected to the installation inputs in O of the second register, first and second D displacement gistrov, third-party setup input, first entry the home of the OR element and the input of the first delay element, the output of which is connected to the information input of the second shift register; the output of the clock generator through the second delay element is connected to the clock input of the associative memory unit, the recording resolution input of the first register, the second input of the third And element and the third input the delay element, the bit outputs of the second shift register and the bit outputs of the third register are connected respectively to the bit analysis resolution input and the analysis resolution inputs and reading the codes of the associative memory block, the output of the third delay element is connected to the shift enable input of the second shift register and the second inputs of the first and second And elements, the outputs of the first and second And elements are connected respectively to the write resolution input in tp-th and left-shift (t is the size of the numbers in the block associative 5 .13 memory) and the write resolution input in the (t + -1) -th bit and right shift of the first shift register, the second input of the OR element is connected to the output of the second AND element and the input of the recording resolution of the second register, the OR element output is connected to the installation input in About the first register, the n-th bit output of which is connected to the input of the m-th digit of the first shift register, the output of the m-th digit of which is connected to the second input of the (nl) -ro element OR of the group, the input (m + D- ro bit first register 0010 1011 0111 0111 001 011 011 011 Editor N.Gorvat. Compiled by V. Orlov Tehred L.Oleynik Proofreader M.Pojo Order 1893/46 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, -. Moscow, Zh-35, Raushsk nab.d 4/5 Production and printing company, Uzhgorod, Proektna, 4 06 the shift is connected to the output of the More threshold element, the input of the subtractor and the control input of the switch, the information inputs of the second group of which are connected to the discharge information outputs of the subtractor, the output resolution of which is connected and the input of the subtraction of the counter to the output of the third element I, the input of the initial installation of the counter is the input of the initial setting of the average arithmetic unit; the output of the counter is the output of the device. Table 1 table 2