SU404077A1 - CONVERTER OF THE RIGHT BINARY-DECIMAL CRUSHES TO BINARY CRACKS - Google Patents

Description

one

The invention relates to automation and computing and is intended for the sequential conversion of codes of regular fractions.

A device is known that performs the conversion of a correct binary-decimal fraction into a binary fraction containing a shift register of static triggers, divided into tetrads, an analysis circuit and a shift, an offset, and a correction circuit.

In the proposed device, in order to simplify and improve its speed, the intermediate outputs of the delay line are connected to the inputs of the correction circuit, the inputs of the AND element are connected to the intermediate outputs of the pulse distributor and the delay line, and the output of the AND element is connected to the input of the binary number register.

The drawing is a diagram of the proposed device.

The device contains: line 1 delay; one-bit adder 2; register 3 binary numbers; correction circuit 4; distributor 5 pulses; element “And 6; bus 7 control pulses; The start signal input 8. For the implementation of the functional units of the device, schemes 9-13 are used; the elements of “Equilibrium 14 and 15; elements “Prohibition 16 and 17; cumulative elements (eg, triggers) 18.

The delay line 1 with a single-digit adder 2 connected in series with it forms a circulation register intended for storing the initial binary-decimal number as well as intermediate results of the shift. Register 3 of the binary number also represents a circulation register of accumulative elements, to which the transformed binary bits are subsequently received. Both circulation registers should have periods of multiples of four. To maintain the same accuracy of the binary fraction, the binary number register can contain 1/4 Ig2 numbers

elements of the register of the binary-decimal number, but in this case the period of the inversion of the register of the binary number must be a multiple of the transfer of the register of the binary-decimal number. In other words, both registers, for example, can be equal to each other, or register 3 can be half as long as a circulation register consisting of a delay line 1 and a one-bit adder 2. The structure of a circulation register has

the distributor has 5 pulses, the circulation period of which is equal to four cycles, and at the time of rebuilding - three cycles.

The device uses the method of shift and correction, which consists in that the initial binary-decimal number is sequentially multiplied by two (by shifting to the left, i.e. towards the higher bits), with the selection of the bits of the integer part, forming the desired binary number. Moreover, those tetrads that are greater than or equal to "5" are adjusted before the shift by adding the number "3 to them. The device works as follows. Binary-decimal digits of the original number / U: l, 2 2 2 2 1, where b is a binary digit (“O or“ 1 ); k is the decimal point number of the correct decimal fraction after the decimal point; p is the binary digit number of the binary-decade tetrad. At the same time, a single control pulse is fed through bus 7 to the pulse distributor 5. Correction circuit 4 determines those tetrads for which 2 6-2 5 occur. This is dried as follows. In scheme 9, coincidence patterns of correction circuit 4 are outputted from a distributor to 5 tetrads for the presence of bits with a weighting factor (i.e., tetrads are detected equal to "8 or" 9). The coincidence circuit 10 produces pulses for tetrads containing the numbers "5," 6, or "7. In the cases that satisfy condition (2), the circuit 4 sends the correction code "0011 (in decimal expression" 3) to the one-digit adder 2, where the addition of the contents of these tetrads with the correction code is carried out. This compensates for the error resulting from the subsequent shift (multiplied by two) of binary-decimal numbers. The shift of the initial number (and subsequently the partial producers) in the circulation register consisting of the delay line 1 and the adder 2 is accomplished by shortening one cycle of the control pulse reversal period in the distributor 5. This occurs every time at the end of the cycle correction, when the element 16 of the Prohibition 16 and the coincidence circuit 11 receives a pulse from the output of the distributor 5. At the same time, the pulse from the output of the circuit 11 coincidence on the element of the Prohibition 17 erases the binary bit that has passed into the integer part of the number code, and t "AND 6 into register 3 as the next bit of the binary number is sent" 1 if condition (2) is satisfied, and "O - in the opposite case. By rebuilding the pulse transmission circuit in the distributor 5, the allocated binary bits of the generated number are set ahead of the previously obtained bits. Consequently, the binary number will circulate in register 3 with the least significant bits ahead. The entire conversion process requires as many cycles as the bits have the output binary number. Subject of the Invention A regular binary fraction decimal fraction converter containing a delay line whose output is connected to the input of a one-digit adder, and a single-digit adder output is connected to the input of the delay line, a correction circuit whose output is connected to the input of a one-bit adder, distributor pulses, the output of which is connected to the intermediate input of the correction circuit, the binary number register and the AND element, characterized in that, in order to simplify the device and increase its speed, weft delay line outputs connected to the inputs of the correction circuit, input element "and connected to the intermediate outputs of the pulse distributor and the delay line and the output member" and is connected to the input of the register a binary number.