SU758152A1 - Device for dividing decimal numbers - Google Patents

Description

The invention relates to computing and can be used in arithmetic devices that process binary and binary-decimal information. five

A division device containing an adder, registers of a private and a divider and a control unit is known in which information outputs of the register of a divider are connected to information 10 inputs of an adder, the output of the sign of the result of which is connected to the input of the sign of the control unit, the first output of which is connected to the input of permitting reception of the next adder operand ,} 5 second output - to the input "shift" of the adder and the register of the private, the third output - to the input of the unit installation of the register of the private, the fourth and fifth output, dy - to the outputs of the forward and reverse 20 ( a divisor register [Ts.Odnako this device can only work with the binary codes;

The closest technical solution to the invention is a device for dividing decimal numbers, containing an adder, a private register, a divider register, a control unit, the input of which is connected to the output of the adder result symbol, the first

The output of the control unit is connected to the enable input of the next adder operand, the second! output - ςς the input "shift" of the adder and the private register, the third output - to the input "+1" of the private register £ 2].

In this device, it is necessary to spend a lot of time to perform addition and subtraction of decimal numbers due to the fact that after binary addition (or subtraction) of the decimal content of the adder and divider, corrective operation is required in separate adder tetrads depending on the type of operation and the occurrence or non-occurrence of transfer from this tetrad.

The aim of the invention is to increase the speed of the device.

This is achieved due to the fact that the correction node is additionally introduced into each tetrad of the divider register, each of which contains seven OR elements, sixteen AND elements and a transfer trigger, with the first and second information outputs of the first digit of the corresponding tetrad register divider being connected to the first inputs first and second elements AND node

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The first information output of the second digit of the corresponding tetrad of the divider register is connected to the first inputs of the third, fourth, fifth and sixth elements And, the second information output of the second digit of the corresponding tetrad of the register of the divider is connected to the first inputs of the seventh, eighth, ninth And elements and to the first input of the first element OR, the first information output of the third digit of the corresponding tetrade of the register of the divider is connected to the first input of the tenth element AND, the second inputs of the ninth, fourth and above the hundredth element of the corresponding tetrade of the register of the divider is connected to the second input of the first element OR, the first input of the eleventh element is And, the second inputs of the fifth and eighth elements of And, the first informational output of the fourth digit of the corresponding tetrad of the register of the divider is connected to the first input of the twelfth element I and the third input of the sixth element I, the second information input of the fourth digit of the corresponding tetrad of the register of the divider is connected to the first input of the trinad the central element And the third input of the first element OR, the second inputs of the first, tenth, twelfth, third inputs of the ninth, fifth and fourth input of the sixth elements And connected to the output of the sign of the control unit, the second inputs of the second, eleventh and thirteenth, the third inputs of the fourth, eighth, The first input of the fourteenth elements And connected to the output "+" of the control unit, the second inputs of the third, fourteenth, third inputs of the tenth, twelfth, fourth inputs of the fourth, eighth elements * And connected to the direct output of the trigger transfer and the first input of the fifteenth element And the inverse output of the transfer trigger is connected to the first input of the sixteenth element And, the third inputs of the eleventh and thirteenth elements And, the fourth inputs of the fifth and ninth, the fifth input of the sixth elements And, and the second input of the seventh element And, the first inputs of the second and the third OR elements are connected, respectively, to the outputs of the fifteenth and sixteenth elements and the subsequent correction node, the second inputs of which are connected to the transfer output of the corresponding tetrad of the adder, t Own in ·. Dyes of the fifteenth and sixteenth elements AND are connected to the second output of the control unit, the outputs of the thirteenth, twelfth *, fourteenth and sixth elements AND are connected to the inputs of the fourth, OR element, the output of which is connected to the information input?

up to the fourth digit of the corresponding tetrad of the adder, the outputs of the eleventh, tenth, fifth, ninth, eighth and fourth elements of AND are connected to the input of the fifth element OR, the output of which is connected to the information input of the third digit of the corresponding tetrad of the adder, outputs of the seventh and third elements And are connected to the input of the sixth element OR, the output of which is connected to the input of the second digit of the corresponding tetrad of the adder, the output of the first and second elements AND are connected to the input of the seventh element OR, the output of which connected to the input of the first digit of the corresponding tetrad of the adder.

FIG. 1 shows a block diagram of a decimal operand divider for 4-digit decimal numbers represented in a 8.4, 2.1 binary-decimal coding system; FIG. 2 is a diagram of the correction unit.

The proposed device contains a binary adder 1, consisting of four tetrads, having information inputs for receiving the tetrads of the next operand, transfer outputs of each tetrad, on which signals appear when transfer occurs from the corresponding tetrads of the adder in the process of binary addition of the contents of the adder with the codes arriving at its information inputs, the enable input of the next operand to add it to the contents of the adder, the output of the result sign, the signal which determines the sign of the sum of the sum Ator, input "shift", the appearance of the signal which provides the contents of the adder shift left four binary digit;

private register 2, containing a set of tetrads by the number of bits of the operand, having an input “+1” for adding a unit to the low-order tetrad, made in the form of a counter, an input “shift”, the arrival of a signal which shifts the register contents by four binary digits to the left;

register divider 3, providing storage of the divider, consisting of a set of tetrads by the number of decimal digits, each of which has an information output for issuing its contents;

a control unit 4 having a sign input connected to the output of a result symbol of the adder, a first output connected to the receive enable input of the next operand of the adder, a second output connected to the shift inputs of the adder and the private register, the third output connected to the ”+1” register input private; paraphase outputs "+" and

single-type correction nodes 5,6,7,8 ,.

the number of which is equal to the number of decimals;

five

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bits, each of which has an information input connected to the corresponding output of the register of the divider, and an output connected to the information input of the corresponding tetrad of the adder, the input of the readdressing permission, connected to the shift input of the adder, the transfer input connected to the transfer output of the corresponding tetrad of the adder, input of the redirection, forwarding output connected to the forwarding input of the correction node corresponding to the nearest high tetrad, the sign inputs connected respectively to the outputs of the block management.

The correction node provides for the correction of the content of the corresponding tetrad of the divider depending on the signals at its inputs "+" or the absence (P) or presence (P) of the transfer at the transfer input. If the input “+” receives a signal, and there is no signal at the output of the transfer of the same node, then this node transmits the divider tetrad to the corresponding information input of the adder without change. If signals are simultaneously present at the input and the transfer input, then the correction node ensures the transfer to the adder of the inverse code of the contents of the corresponding tetrad of the register of the divider. If there is an input signal

and there is no signal at the input of the · transfer, then the contents of the corresponding tetrad of the register of the divider are transmitted to the adder by this correction node in the form of a return code (inverse code reduced by six). If there are (P) and "+ ^n, then the value of the tetrad is increased, increased by 6. By the signal at the input of the forwarding permission, the transfer signal from the ϊth tetrad is assigned to the (4. +1) node through the corresponding inputs and outputs of the forwarding of the correction nodes. corrections to ensure the transfer to the adder at the next addition cycle - subtraction of the (r +1) -th tetrad register divider.

The division is performed in η cycles, the number of which is determined by the width of the representation of decimal numbers.

On each cycle, the definition of one decimal digit of the private, starting with the oldest.

Each cycle consists of a sequence of operations of subtracting or adding a divider to the contents of the adder.

The device works as follows.

In the initial state in the adder is the value of the dividend, in the register of the divider - the value of the divider, at the inputs of the transfer of transfer nodes are set units.

At the beginning of the first cycle, a signal appears at the outputs of the control unit. The signal from the output of the control unit enters the inputs of all the tetrads of the divider from the register of the divider. The adder, having at its input a signal to enable reception of the next operand, ensures the reception of the code arriving at its information inputs and its binary addition with its contents. The sign of the amount received is transmitted to the input of the sign of the control unit. The control unit analyzes this sign. If the sign is positive, the control unit generates a signal at its output, providing an increase in the contents of the lower tetrad of the private register by one and generates signals at its outputs, ensuring the beginning of the second cycle of the current cycle. The signal from the output of the control unit enters the corresponding inputs of the correction nodes, ensuring the transfer of the contents of the tetrads of the code register in the inverse or inverse code. At that, the correction node corresponding to the adder's tetrad, where the transfer occurred at the previous clock (ie, the correction node that received the transfer input signal), transfers the contents of the corresponding adder tetrad in the inverse code, and the correction node corresponding to the adder tetrad, where the previous cycle, the transfer signal was absent (i.e., a correction node that did not receive a signal at its transfer input), ensures the transfer of the contents of the corresponding tetrad of the register of the divisor in the reverse code. The adder performs a binary addition of its contents with the code arriving at its information inputs. The sign of the amount received is transmitted to the control unit.

If the sign is positive, a signal is produced at the output of the control unit. In addition, signals appear on the outputs of the control unit, which ensure the execution of the next cycle, etc. Such cycles are repeated until, after the next cycle in the adder, a negative number is not obtained. In this case, the control unit, having received a corresponding signal at its outset, does not generate a signal at its output, but organizes a recovery cycle for the remainder by generating signals at its outputs. Having received a signal at its input "+", each ^! The second correction node transmits to the information input of the adder the contents of the corresponding tetrad of the divider register in the direct code, if there was no transfer in the previous cycle in the corresponding tetrad of the adder (if this correction node did not have a signal at its transfer input), or produces

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• the transfer of the direct code of the contents of the corresponding tetrad of the register of the divisor increased by six to the information input of the adder (if a transfer occurred at the previous clock in the corresponding tetrad of the adder), i.e. _ This correction node for its inlet- ⁵ de transfer had a signal.

After the addition to the recovery cycle, the control unit organizes the transition to the next cycle. At the same time, it produces a signal at its output,

This signal, acting on the inputs of the shift of the private and the adder, provides a shift of their contents by four digits to the left. In addition, the same signal, arriving at the entrances of the redirection permission of all correction nodes, provides, by the corresponding redirection inputs, an assignment to any (-уз +1) th node of the transfer signal correction that arrives at the ίth correction node, 20

to control the upload in the next cycle of subtracting the value (ί + 1) -οή of the tetrade of the divider register into the adder.

After the shift, the next division cycle begins to determine the second quotient of the quotient. This cycle is performed exactly as the first one, but at the first clock cycle the transfer of the contents of the tetrads of the divider register is carried out under the control of the redirected transfers that occurred during the recovery cycle of the first cycle. All subsequent cycles are performed in the same way as the second cycle.

The considered division device allows to reduce the time spent on finding the quotient, due to the fact that when summations of decimal numbers are performed in the process of implementing the division of decimal operands, no additional operations of correction of the adder content are performed.

Blocks 1-4 can be considered traditional blocks of known dividing devices. Correction nodes of the same type

45

5-8 are specific to this device.

The table shows the codes generated by the correction node, depending on the code arriving at its information input, from the "+" signals,

coming from the control unit, and the signal at the transfer input. The values of, respectively, the first (junior), second, third and fourth digits of the tetrad code at the information input of the correction node are denoted by A., A ^, A ₄ , and C ₄ , C _g , St, C ₄ - respectively, the first, second, third, fourth digits of the tetrad code at the information output of the correction node, symbol 5 and P denote, respectively, the "+" signals coming from the control unit of the dividing device, P and P denote the presence or absence of the transfer signal at the transfer input of the correction node .

Based on the above table, you can write the following logical expressions for С ₁ , С ₂ values,,

Sd:

WITH! - А ^ УЙР

C _a - A, PUAP

S, -PAULLPR \ / (AD) / ^) ^Ryu (AAH ^) P5 C ^, -A ^ ZUA ^ RU (/ ^ uD ^ PRUOy / А ^ ПЗ

FIG. 2 shows a diagram of a correction node that implements data and relations. It consists of the following elements:.

- accordingly, the first is the seventh elements OR 9-15;

accordingly, the first - the sixteenth elements And 16-31)

- the first and second (inverse and direct) information outputs 32, 33 of the first (lower) digit of the corresponding tetrad register divider, connected to the first inputs of the first and second elements 16, 17, respectively)

Coda tetrad P P five R five R ^A < • ^A % · ' ^Eh ? ^A 1 Sd; from ₄ ^From 1 -WITH, Sd with _a : since _g WITH, ^from 4 with _a ^From 2 :WITH/ Sd <4 •WITH, ;with, 0 0 0 0 0 1 one 0 one one one one 0 0 0 0 one 0 0 one 0 0 0 one 0 1 one one one one one 0 0 0 0 one one 0 0 0 0 0 one 0 ten 0 0 one one 0 one 0 0 one 0 0 one one one 0 0 one • one ten 0 one one one 0 0 0 0 one one 0 one one 0 0 one 0 0 ten one 0 one 0 one one 0 one 0 0 0 one 0 one 0 one 0 one ten one one one 0 one 0 0 one 0 one 0 one 0 0

9

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Table continuation

Tetrade codes ί one I five R • five .....four . R ^ 4 * ⁴ l. / C ₂ - C, C y: C _g C, with „. · С,: с _г : с, C </ ’C Λ · C 4 .’C,

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the first and second information outputs 34, 35 of the second discharge of the corresponding tetrad of the register of the divider, with the first output connected to the first inputs of the third, fourth, fifth and sixth elements And 18, 19, 20,

21, and the second output - to the first inputs of the seventh, eighth, ninth elements And 22, 23, 24 and to the first input of the first element OR 9;

- the first and second information outputs 36, 37 of the third digit of the corresponding tetrad of the register of the divider, with the first output connected to the first input of the tenth and second inputs of the ninth, fourth and sixth elements And 25, 24, 19, 21, and the second outlets to the second input of the first element OR 9, the first input of the eleventh and second inputs of the fifth and eighth elements And 26, 20, 23?

- the first and second information outputs 38, 39 of the fourth category of the corresponding 40 tetrad of the divider register, the first output being connected to the first input of the twelfth and third input of the sixth element And 27, 21, and the second output - to the first input of the third and third elements And 28 and to the third entrance of the first element OR 9;

-outputs of the sign and "+" <Р, 5) 40,41

control unit, respectively, with the output 40. connected to the second inputs of the first, tenth, twelfth, third inputs of the ninth, fifth and fourth input of the sixth elements And 16, 25, 27, 24, 20, 19, 21, and the output 41 "+" the control unit is connected to the second inputs of the second eleventh and $ 13 th and thirteenth, the third inputs of the fourth, eighth, the first input of the fourteenth elements And 17, 26, 28,

19, 23, 29;

-trigger transfer 42, direct and in- £ 0, all of the inputs are connected to the outputs of the second and third elements OR 10, 11, the direct output of the transfer trigger 42 is connected to the first input of the fifteenth element And 30, the second

the inputs of the third, fourteenth, third inputs of the tenth, twelfth, fourth inputs of the fourth and eighth elements And 18, 29, 25, 27, 19, 23, and the inverse output of the transfer trigger is connected to the first input of the sixteenth, second input of the seventh, third inputs of the eleventh and thirteenth , the fourth inputs of the fifth and ninth, the fifth input of the sixth elements And 31, 22, 26, 28, 20, 24, 21;

- paraphrase redirection inputs 43, 44, connected to the first inputs of the second and third elements OR 10,11

-paraphrase output forwarding 45-, 46, connected to the outputs of the fifteenth and sixteenth elements And 30, 31 of this node correction and to the redirection inputs of the neighboring senior node of the correction;

- paraphrase output 47, 48 of the transfer of the corresponding tetrad of the adder "connected to the second inputs of the second and third elements OR 10, 11;

- the second output 49 (shift output) of the control unit connected to the second inputs of the fifteenth and sixteenth elements I 30, 31;

-the input of the first 50 (low) digit of the corresponding tetrada of the adder, connected to the output of the seventh element OR 15, the first and second inputs of which are connected, respectively, to the outputs of the first and second elements AND 16, 17;

- the input of the second digit 51 of the corresponding tetrad of the adder, connected to the output of the sixth element OR 14, the inputs of which are connected to the outputs of the third and seventh elements μ 18, 22;

- input 52 of the third digit of the corresponding tetrad of the adder, connected to the output of the fifth element OR 13, whose inputs are connected to the outputs of the eleventh, tenth, fifth, ninth, eighth and fourth elements (26, 25, 20, 24, 23, 19),

-Input 53 of the fourth category respectively

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v'tetvukvdey tetrad adder connected to the output of the fourth element OR 12, the inputs of which are connected to the outputs of the thirteenth, twelfth, fourteenth and sixth elements And 28, 27, 29, 21.

This correction node performs all the necessary shipments given when describing the operation of the decimal operand divider, provided that in the initial state, before the start of the first division cycle to determine the most significant bit of the required quotient in the transfer fixation trigger of each insertion node, a single value is set.

Claims (1)

Claim A device for dividing decimal numbers containing an adder, a private register 20., a divider register, a control unit whose input is connected to the output of the adder result sign, the first output of the control unit is connected to the receive enable input of the next 25 operand of the adder, the second output to the input "shift" and the adder regist-, pa private third output - to the input of "one" private register, characterized in that, in order to improve device performance, it contains ³ to each tetrad divisor register correction unit, each of which comprises t seven elements OR, sixteen elements And and trig--, the transference ger,. the first and second information outputs of the first discharge of the corresponding tetrad of the register of the divider are connected to the first inputs of the first and second elements of the correction node, the first information output of the second discharge of the corresponding tetrad of the register of the divider is connected to the first inputs of the third, fourth, fifth and sixth elements And, second information output of the second discharge- '45 yes the corresponding tetrade of the register of a divider is connected to the first inputs the seventh, eighth, ninth elements And to the first input of the first element OR, the first information output of the third digit of the corresponding tetrad of the register of the divider is connected to the first input of the tenth element And, the second inputs of the ninth, fourth and sixth elements And, the second information output of the third digit respectively-55 the corresponding tetrad of the divider register is connected to the second input of the first element OR, the first input of the eleventh AND element, the second inputs of the fifth and eighth AND elements, the first informational 60 register number corresponding tetrad divider is connected to the first input of the twelfth AND gate and a third input the sixth element And, the second information input of the fourth digit of the corresponding tetrad of the register of the divider is connected to the first input of the thirteenth element AND and the third input of the first element OR, the second inputs of the first, tenth, twelfth, third inputs of the ninth, fifth and fourth input of the sixth element AND are connected to the output of the sign control unit, the second inputs of the second, eleventh and thirteenth, the third inputs of the fourth, eighth, the first input of the fourteenth elements And connected to the output "+" of the control unit, the second inputs of the third , the fourteenth, the third entrances of the tenth, the twelfth, the fourth entrances of the fourth -. In addition, the eighth And elements are connected to the direct output of the transfer trigger and the first input of the fifteenth element And, the inverse output of the transfer trigger is connected to the first input of the sixteenth element And, the third inputs of the eleventh and thirteenth elements And, the fourth inputs of the fifth and ninth, fifth input of the sixth element And the second input of the seventh element AND, the first inputs of the second and third elements OR are connected, respectively, to the outputs of the fifteenth and sixteenth elements AND the subsequent correction node, the second inputs of which are under Linked to the transfer output of the corresponding "tetrad of the adder, the second inputs of the fifteenth and sixteenth elements And · connected to the second output of the control unit, the outputs of the thirteenth, twelfth, fourteenth and sixth elements And connected to the inputs of the fourth element OR, the output of which is connected to the information input of the fourth digit corresponding the tetrads of the adder, the outputs of the eleventh, tenth, fifth, ninth, eighth and fourth elements of AND are connected to the input of the fifth element OR, the output of which is connected to the infor to the third-party copy input of the corresponding tetrad of the adder, the outputs of the seventh and third elements AND are connected to the input of the sixth element OR, the output of which is connected to the input of the second digit of the corresponding tetrad of the adder, the outputs of the first and second elements AND are connected to the input of the seventh element OR? the output of which is connected to the input of the first digit of the corresponding tetrad of the adder.