SU1238058A1 - Shifting device with check - Google Patents

Abstract

The invention relates to the field of computing, in particular to digital parallel shifters used in processors of small and medium-sized computers. The aim of the invention is to reduce hardware costs. To achieve this goal, a device containing a shift block, a block group, a shift, a register, a trigger, a comparison circuit, a group of shift registers, the first and second groups of elements EXCLUSIVE OR, and a group of switches, contains the third and fourth groups of elements EXCLUSIVE OR and the block of elements I. 1 il. with S op OO oo sd 00

Description

one

The invention relates to computing technology, and more specifically to digital parallel shifters used in processors of small, medium-sized computers.

The purpose of the invention is to reduce hardware costs.

The diagram shows the layout of the device for shifting with control.

The device for shifting with control contains a group of 1 shift blocks, a group of shift registers 2, a group of 3 elements EXCLUSIVE OR, a clock input 4 of the device, an input 5 specifying the device mode, an output 6 of the device, a group of 7 elements EXCLUSIVE OR, a group of switches 8, groups 9, 10 elements EXCLUSIVE OR, block 11 elements AND, register 12, comparison circuit 13, trigger 14, input 15 of the left sliding device, information information input 16 of the device, input J7 of the device shift code, input 18 of the device shift type, input 19 device sign, input 20 right th device's sliding bit, information output 21 of the device, output-22 of the control bits of the device, shift block 23.

The shifter with control works with a widespread 64-bit data format that has a byte structure with one check bit per byte.

The 1 shift unit is a set of one-way radios according to the following table:

shift o

I

Executable function

Spread to all outlets

sign on

ABOUT

about

about

about

I

Blocking of outputs (filling with units) Shift to the left in the additional code

Shift to the right in the additional code

Shift cyclical right Shift cyclical left

Arithmetic right shift

Arithmetic left shift

five

1238058J

The shift unit 1 performs shifts by the number of bits a multiple of four and is implemented similarly to the prototype.

Shift register 2 performs shifts 5 per bit per clock as follows:

Control Code Mode

Storage Shift Right Shift Left Reception Data

The shifter with the control can perform the following operations: tetrad or byte shift; parallel-serial shift; sequential shift.

At the beginning of the time cycle of operation, input code 18 sets the code for the required operation 1I, input number 17 the code of the number of shifts, and input 19 the sign of the number. Input 5 sets the receive mode. At the input 16, the input data is set, which is fed to the inputs of the group 1 shift blocks, where they are shifted by a given number of bits in accordance with the sign and type of shift. The input data from the device input 16 also goes to a group of 3 EXCLUSIVE OR elements, where they are minimized and fed to the input of the shifter 23, where they are shifted by the same number of bits as the input data. The shifted input data in accordance with the value of input 5 of the device is received in the shift register 2. From the output of the shift block 23, the values arrive at a group of 9 EXCLUSIVE OR elements, where the values of the control bits of the bytes are formed, which pulse from the input 4 of the device passes through the block II of the elements AND and entered through the setup inputs to the trigger 12 register.

The shifted data is fed to the output 21. data, and the control bits for them, generated on the elements EXCLUSIVE OR 7, go to the output 22.

When the device is working properly, the generated code on the elements 7 and the code obtained as a result of the shift in register 12 must match. AT

otherwise, a comparison signal is generated in the comparison circuit 13, according to which the trigger 14 is set.

Parallel-sequential shifts are used to perform data shifts for any number of bits from 0 to 63. This operation is mainly used to execute logical and arithmetic shifts.

Shifts to an arbitrary number of bits are performed in one or two micro-command loops, the first of which performs tetradetic and one (none) single-time shifts, and in the second cycle, two one-time shifts are performed. The number of cycles and actions in them are determined by branching in the microprogram by two lower digits of the shift code. If the shift mode at input 5 of the device is set, a single shift of data in register 2 is performed. The data shifted between the bytes is allocated on the switches 8, while the shift 8 to the left is controlled by the high-order, and when shifting to the right - the lower-order input 5 device.

Input elements EXCLUSIVE OR 10 receive pushed and pivoted bits for each register 2. If at the input of any element 10 the signals of the input and output shifted bits do not match, then the output signal fails. These signals arrive at the counting inputs of the corresponding triggers of register 12 and invert the check bits of the corresponding bytes. After the completion of successive shifts, the codes in register 12 and those generated on elements 7 must match. Otherwise, a failure is detected on the trigger 14.

In a sequential shift operation, the shift registers 2 can be used to store and shift the multiplier and accumulate the product and quotient. Preliminary source data can be loaded into register 2 at zero number of offsets, as described in the byte shift operation.

Claims (1)

Invention Formula A control shift device containing a shift block, a block group 5 0 5 50 five 0 five 0 shift, register, trigger, comparison circuit, group of shift registers, first group of elements EXCLUSIVE OR, second group of elements EXCLUSIVE OR, and group of switches, moreover, the information input of the device is connected to the Information inputs of the blocks of the shift group, the outputs of which are connected respectively to the information inputs of the shift registers the groups whose mode inputs are connected to the control switches of the group switches and to the input of the device mode setting, the inputs of the shift code, the type of shift and the sign of which are connected to the corresponding inputs of the group shift block and the shift block, the outputs of the group shift registers are the information output of the device, the outputs of the EXCLUSIVE OR of the first group are connected to the information input of the shift block, the outputs of the group of shift registers are connected to the inputs of the corresponding EXCLUSIVE OR of the second group, whose outputs connected to the first group of inputs of the comparison circuit, the second group of inputs of which is connected to the outputs of the register, the output of the comparison circuit is connected to the trigger input, the output of which is A device output, characterized in that, for the purpose of reducing hardware costs, it contains a third group of EXCLUSIVE OR elements, a block of AND elements, a fourth group of EXCLUSIVE OR elements, and the bits of the information input of the device are connected respectively to the inputs of the EXCLUSIVE OR elements of the first group , the outputs of the shift block are connected respectively to the inputs of the EXCLUSIVE OR elements of the third group, the outputs of which are connected to the information input of the AND block whose control input and output are are united respectively with the clock input of the device and the setup input of the register, the counting inputs of the flip-flops of which are connected to the outputs of the corresponding elements EXCLUSIVE OR of the fourth group, the first and second inputs of the k-ro element EXCLUSIVE OR of the fourth group (k 1 g, n is the number) about With the k-ro and (k + l) -ro outputs of the group switches, respectively, the inputs of the sheavoid and left retractable bits are in the devices are connected respectively to the right bit inputs of the k-ro and left bits of the first group shift registers, the input and output of the right bits of the k-ro group shift register are connected respectively to the output and input of the left bit of the (k + 1) th shift register the groups, the outputs of the left bits of the group registers and the input of the right-moved | bit device are connected respectively to the first information inputs of the group switches, the input of the left-sliding device bit and the outputs of the right bits of the group shift registers are connected respectively Consequently, with the second information inputs of the group switches, the outputs of the EXCLUSIVE OR elements of the second group are the output of the control bits of the device. ff 23  L p k " Compiled by A, Klyuev, Editor M. Tovtin Tehred.Hodanich Proofreader L. Patay Order 3292/49 Circulation 671 Subscription VNIIPI State Committee: the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4