SU1439580A1 - Device for simultaneous subtraction of two polynominals - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to increase the speed of the device. The octal sign of d-number is used to number the system to represent the two-row code of partial re-I атов I tats, / and the device contains (- + 2) time blocks, in each of

Description

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with sd

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ffVutnn g woo x

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which have a multiplier register 1, a partial result register 2, a first 3, a second 4, a third 5 and a fourth 6 triggers, a carry register 7, a switch 14, an adder 17 and a paired block 1 8o And the information inputs of the somnolitel 1 register and the partial result register 2 of the first computational block are inputs: device Inputs for triggers 3-6 i-ro

one

The invention relates to digital computing and can be used in the construction of computing systems.

The aim of the invention is to increase the speed

The drawing shows a block diagram of the device

The device contains computational blocks that include registers 1, somnoelteles, registers 2 partial results js, triggers B-B, registers of 7 transfers, register 8 of results, registrar 9 of transfers of result ;, a group of elements of the ARM 0 CEE 10, elements OR 11-135 switch 14, groups of elements I 15, groups of one-digit adders 16 ;, 17o combinational adders In addition to the device, there are memory blocks 18, a slalmator 19 results, a one-bit adder 2

The device works as follows

In the first clock cycle, in the first computational block, the zero code is fed to the inputs of register 1, the partial result code — the code of the number a — is input to the multiplier 2 (about the first clock input to the first bit of the control input, a setup signal is given. Hera 3, in the second cycle to the input of the second discharge of the control input and

so on to (- + 2) th tact On

the third cycle to the input of register 1 with the multiplier X is given, to the input of register 2 of the partial result aj Loading opera1 1 of one Horner circuit continues similarly up to

(2k n-1) th cycle5 when accepted

the computing unit is connected to the outputs of the memory block 18 (i + 1) of the computing unit, the outputs of the flip-flops 3-6 are connected to the control inputs of the switch 14, the outputs of the adder 17 to the inputs of the memory block 18 and to the information inputs of the partial result register 2 and the transfer register 7 (i + t) -ro of the computational unit of 1 GoP, files, 1 ill.

0

the last two operands x and a “about (2k + 3) -th cycle at the input, register 1 factor must be given the code 00,„. 01, and the input of the register 2 partial result is the code of the kul. An additional result code appears at (+ 2) clocks at the outputs of the result adder 19

The operands of one polynomial are loaded at odd numbers. On even cycles, operands of another polynomial are loaded. Thus, two polynomials are calculated simultaneously.

Claims (1)

Invention Formula 1c A device for simultaneously calculating two polynomials, containing - + 2) computing blocks (where n is the code width of the argument) each of which contains a multiplier register, a partial result register, a combinational adder, first to third triggers, a switch; all of the sequential blocks, except the first one, contain a memory block, and in each computing block, the trigger synchronization inputs from the first to the third J register multiplier and the partial result register are connected to the clock input of the device, the output of the multiplier register i-ro of the computing block, where i 1, 2 , PC , 0,5 -5- and, is connected to the information input of the register of the multiplier (i + 1) -th block, characterized in that, in order to increase speed, a result register, a result transfer register, a result adder are entered into it, a quarter trigger is inserted into each computing unit, from the first to the third elements I, n 4 - 7 elements EXCLUSIVE OR, a group of one-digit adders, a group of elements AND, and the one-digit adder is entered into the first computing unit, into the computing blocks with the second three bits in the direction of the iIIh bits are connected to the inputs of the corresponding But register partially the result and the transfer register of the (i + 1) -th computational block, the most advanced bit The 20 gist of the partial result of the (i + 1) -th supervisory unit is connected to the output of the fifth digit of the combinational adder of the i-ro computing unit, the information inputs from the first to Go to (- + 2) - and entered the register re ™ I In each computational block, the bits of the register of the multiplier are connected to the first inputs of the corresponding EXCLUSIVE SHSh elements, the output of the first trigger is connected to the second & and the inputs of the EXCLUSIVE OR elements and to the first inputs. From the first to the third elements, AND, EXTERNAL 25 quarter-time triggers of the i-ro calculator; the moves of the elements EXCLUSIVE 11PI of the connecting unit are connected to the outputs with a shift of one to four bits, respectively, from one to four times younger: Dows from the first information block of the memory block of the (i + 1) -th computational input of the switchboard and the power supply unit, the output of the sum and the non-shift by two bits in the direction of the young spreads of the combinational adder /P (+ 2) -th computational block of dry bits with the second information input of the switch, the code of the 1st element EXCLUSIVE RSHI (where 1 1, 2, are united with the information inputs of this is about 5) J is connected to the first input of the responsible register the result and the 1st element AND group, the output of the second result transfer register, the clock inputs of the result registers and result transfers are connected to the clock input of the device, the outputs of the result register and register of the transfer 40 results of the result are connected respectively to the first and second inputs of the adder In the first computing unit, the output of the sum is connected to the corresponding input 45 of the (n + 5) -th one-digit adder of the group connected to the first input of the single-bit adder, the output of the third element I is connected to the second input single bit adder. the first trigger is connected to the inputs and inputs of the AND elements of the group and to the second input of the first element AND, the outputs of the third and fourth triggers are connected respectively to the first and second control inputs of the switch, and to the second inputs of the second and third elements AND, the input to the O the first triggered device, the codes of elements And from the first to (n + 6) -and groups are connected to the first inputs of the corresponding one-bit group adders, the output of the (7) -th element And group - gg is the output of the sum of one-bit adders with the first input (n + 7) -th connected to the first input (n + 5) -th bit of the combinational adder, the combinational adder's discharge, the switch bit outputs connected to the single-bit transfer output sum are connected to the second inputs of the corresponding torus with the transfer input of one-bit adders of the group, the gg (n + 4) -th bit of the combinational stroke of the first element I is connected to the adder, the output of the (n + 7) -th bit the partial result register is connected to the second input of the (n + 7) -th bit of the combinational adder, the transfer output of the (n + 7) -th bit of the combinational adder, the output of the second element I is connected to the second 580 the input (n + 6) of the bit of the combinational adder, the outputs of the sum of one-digit adders, ct utty, except for (- (n + 5) -th, are connected to the first inputs of the corresponding bits of the combiner adder groups, where р 2, 3, .о, п + 6, is connected to the second input (p - 1) -th bit of the combinational adder, output is sum10 we, except the senior bit, and the carries of the combinational adder of the i-th computing unit with a shift by three bits in the direction of iIIad bits are connected to the inputs of the corresponding but the partial result register and the transfer register of the (i + 1) -th computing unit, the most senior bit the gist of the partial result of the (i + 1) -th ultra-small block is connected to the output of the fifth digit of the combinational adder of the i-ro computing block, the information inputs from the first to Quarter-type triggers of the i-ro computational unit are connected to the outputs, respectively, from the first to the fourth time, the rows of the memory block of the (i + 1) -th computing unit, the output of the sum and the transfer of the combinational adder /P (+ 2) -th computing unit is connected to informational inputs of the result register and the result transfer register, respectively, the clock inputs of the result register and the result transfer are connected to the device clock input, the outputs of the result register and the result register are connected to the first and the second inputs of the result adder, the output of which is the output of the device, in the first computational unit the output of the adder of the (n + 5) -th one-digit group adder is connected to the first input of one A single adder, the output of the third element I is connected to the second input of a one-bit adder. the (n + 6) th and (n + 5) -th bits of the partial result register are connected to the third inputs (n + 6), respectively, and (n + 5) -th one-bit accumulators of the group, in a m computing unit (a 2,. ,,, m 2) the output of the third element I is connected to the third input of the (n + 5) th one-bit adder of the group; the output of the sum of the (n + 5) -th one-digit adder of the group is connected to the first input of the (n + 5) th bit of the combinational the adders, the outputs of the carry registers are connected to the corresponding inputs of the carries of the combinational adder, the outputs of the higher five bits of the sum and the code transfer combinational adder, connected to the address input of the memory block. 2o The device according to claim 1, about tl and - the fact that in each computing unit is a combination n + 7 adder contains s-bit S adders (s 53), the first 0 and second inputs and the transfer input of the combinational adder are respectively the first and second inputs and the transfer input of the corresponding s-bit totalizer, the outputs of sum 5 and transfer of the combinational adder are respectively the outputs of the sum and transfer of the corresponding s-bit adder.