SU1465883A1 - Device for dividing numbers - Google Patents

Abstract

The invention relates to computing and can be used in the construction of universal and specialized digital computers. The aim of the invention is to reduce hardware costs. This goal is achieved by the fact that the device for dividing numbers containing three registers 2, P, 17, the sumatmator 6, the switch 5, the block 12 of memory, the element OR 13, the elements OR 14, 15, the trigger 8, the adder 16 g are entered links. 2 ill., 1 tab.

Description

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The invention relates to computing and can be used in the development of parallel digital computers. ,

The purpose of the invention is to reduce hardware costs.

Fig. 1 is a schematic diagram of a device for dividing schsel; Figure 2 is a switch bit diagram. .}about

The device of FIG. contains the information input 1 of the device, the first register 2, the input 3 of the initial installation of the device, the input 4 of the control

entering the device, switch 5, 15 is pre-reset to the first adder 6, the first clock signal input 3. The input 4 input 7 of the device, trigger 8, the third clock input 9 of the device, the second clock input W device, the second register 11, block .12 memory, first, 20 second and third elements OR 13-15, second adder 16, third register 17, output 18 of a particular device, output 19 of the sign of a particular device.

The discharge of the switch 5 (FIG. 2) maintains the second control input 20 of the switch 5, the element 21, the output 22 of the switch 5, the element

OR 23, third control input 24., .. „„ ... “

switch 5, element 25, quadruple 30 The divider bit is sequentially controlled input 26 of switch 5, input signal 10 is written to relay element 27, fifth control input 28 of switchboard 5, and 29, the element is NOT 30, the element is AND 31.

The six most significant bits of register 2 and the second, third, fourth significant bits (counted from the highest register 11 are connected to the address inputs of block 12. If we mark the bits of register 2 arriving at the address inputs of block 12, starting from the high bits, the characters О ,, 0, j, О,, 64, О у, arriving at the inputs of the block 12 bits of the register П - У, У4 and the outputs of the block 32 - И1, И2, ИЗ, И4, then its encoding has the form presented in the table .

Switch 5 (figure 2) works

ment And 27 and at output 22 will pass + 4U. The signal I4, arriving at input 28 will open element And 29 and at output 22 of switch will pass -4y. When a signal is applied to the input 4, the inversion signal from the element NE 30 locks the elements 21 21, 25, 29 and the output 22 of the switch 5 through the element 31 passes the dividend from the input 1,

The device of FIG. I works as follows.

The input to the device 1 is the direct code of the dividend X. Register 2

the device is given a single signal, significant digits of the dividend are passed | through the switch 5, the adder 6 to the input of the register 2 without change. According to the signal received at input 7, the significant bits of the dividend are recorded in register 2. At the same time, the sign bit of the dividend is fed to the counting input of the trigger 8, previously (: the leading to zero, and the signal at input 9 is written to it.) divisible by input 1 is fed to my divider code

as follows.

If a signal arrives at the switch input .., then element 21 will open and at output 22, the switch will pass through element OR 23 twice the divider value + 2y. If the input 24 receives a signal, the output 22 through the element And 25 will be the inversion of the doubled divider. I.e. -2u. Similarly, the signal, the inputs to the input 26, will open

gistr i1. The sign bit Y on the signal at input 9 enters the counting input of the Viv trigger last. the sign of the private is formed.

In the first cycle, the high-order bits of the dividend and the divider are fed to the address inputs of block 12, and signals I1, I2, IZ, I4 are formed at the outputs of the block 12. Under the influence of these signals, one of the multiple divisors is formed in the switch -5: + 2y, -2y, -4y, O, This multiple is fed to one input of the adder 6. Deduced (or the next balance) from the outputs of register 2 goes to the other inputs of the adder 6 with a bias of two bits in the direction of the older bit 35

40

Dov, i.e. adder 6 enters, Q is the quadruple value of the dividend (or the remainder 4x. Adder 6, operating in reverse codes, forms the first residual 0. At the same time, the signals from the outputs of memory block 12 are fed to the inputs of the elements OR 13, 14, 15, the output of which Connection to the inputs of the adder 16. Obviously, if I1 1, all units of the adder 16, except for the younger (SMj.), will receive one.

55

previously reset to signal at input 3. Input 4

ment And 27 and exit 22 will pass + 4U. The signal I4, coming to the input 28, will open the element And 29 and on the output 22 of the switch will pass -4y. When a signal is applied to the input 4, the inversion signal from the element NE 30 locks the elements 21 21, 25, 29 and the output 22 of the switch 5 through the element 31 passes the dividend from the input 1,

The device of FIG. I works as follows.

The input to the device 1 is the direct code of the dividend X. Register 2

previously reset to signal at input 3. Input 4

 ., .. "" ... "

 Significant bits of the divider on-signal at the input 10 is recorded in

the device is given a single signal, significant digits of the dividend are passed through the switch 5, the adder 6 to the input of the register 2 without change. The signal arriving at input 7, significant digits of the dividend are recorded in register 2. At the same time, the sign bit of the dividend is fed to the counting input of the trigger 8, previously (: the leading zero, and the signal at input 9 is written to it. When the dividend is written input 1 is fed to my divider code

30 The digit of the digit of the divider by-signal at the input 10 is recorded in the re-

gistr i1. The sign bit Y on the signal at input 9 enters the counting input of the Viv trigger last. the sign of the private is formed.

In the first cycle, the high-order bits of the dividend and the divider are fed to the address inputs of block 12, and signals I1, I2, IZ, I4 are formed at the outputs of the block 12. Under the influence of these signals, one of the multiple divisors is formed in the switch -5: + 2y, -2y, -4y, O, This multiple is fed to one input of the adder 6. Dedemoe (or the next balance) from the outputs of register 2 goes to the other inputs of the adder 6 with a bias of two bits in the direction of the older bit 35

0

Dov, i.e. adder 6 receives the Q quadruple value of the dividend (or 4x residual. Adder 6, operating in reverse codes, forms the first residual 0. At the same time, the signals from the outputs of memory block 12 are fed to the inputs of the elements OR 13, 14, 15, the output of which to the inputs of the adder 16. It is obvious that if I1 1, in all bits of the adder 16, except for the younger (SMj.), one will go.

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those. the adder receives the number -2 IF, the unit enters only the low-order adder (number +2), If, the adder receives the number -4. IF I4, the number +4 enters the adder. The other inputs of the adder 16 are shifted by two bits towards the higher bits of the value of the previous cycle from register 17. Upon completion of the summation operation in adders 6, 16, a write signal is sent to the device input 7, according to which the remainder O is written to register 2 and the first approximation of the quotient ..Z is in register 17 Then the second cycle is performed

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division. Upon completion - cycles with

Exit points 18 and 19 of the device read the quotient.

Claims (1)

Invention Formula A device for dividing numbers containing three registers, a first adder, a switch, a memory block and the first OR element, with the information input of the device connected to the first information input. the switch, the first control input of which is connected to the input control input of the device, the input of the initial installation and the first clock input of which is connected respectively to the reset input and the input of the enable resolution of the first register, the information input of which is connected to the output of the first adder, the input of the first addend is connected to the output of the switch, the informational inputs of the i-ro discharge of which are connected in parallel with the fifth, respectively, with the direct output (iJ) -ro discharge, with the inverter output (C-1) of discharge, with the right m th output (i-2) -ro bit - and with inverse output (i-2) -ro. bit of the second register ((n + 2, p-size of the operands), the input of the reception of which is connected to the second clock input of the device, the first clock input of which is connected to the discharge input of the third register, the output of which is the output of the private device, the outputs of the higher bits of the first and second registers are connected respectively to the first and second address inputs of the memory unit, the information input of the device is connected to the information input of the second register, the output of the first register is connected with a shift by two digits towards the higher bits with the input of the second term of the first adder, о t - l. In order to reduce hardware costs, it contains a second adder, a second and a third OR trigger, and the outputs from the first to the fourth memory block are connected respectively to the control inputs of the second to fifth switch, the information input of the device is connected to the counting trigger input, the enable input of the prim and the output of which are, respectively, the third clock input and the output of the private device sign, the second output of the memory block is connected to the first input of the first element OR the first output of the block the memory is connected to the first inputs of the second and third OR elements, the third output of the memory unit is connected to the second inputs of the first and third OR elements, the fourth output of the memory unit is connected to the second input of the second SHS element, the outputs of the first and second OR elements are connected respectively to the inputs the first and second bits of the first term of the second adder, the output of the third element is connected to the inputs of the bits from the third to the nth first term of the second adder, the output of which is connected to the information input of the third regis tra, the output of which is connected with a shift by two bits towards the higher bits with the input of the second term of the second adder.