SU1287149A1 - Device for dividing numbers - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in the construction of specialized and universal digital computers. To increase the speed of the device, two registers 6 and 8 have been entered into it, memory block 10, two I-RSHI 15, 17 elements, adder 4, switch 9, AND 19 element, OR 18 element 18. 2 ill., 1 tab.

Description

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The invention relates to computing and can be used in the development of digital computers of sequential action.

The aim of the invention is to improve the speed of the device.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 is a timing diagram of device clock signal generation.

The device for dividing the numbers contains the register 1 of the dividend, the first element AND 2, the first clock input 3, the adder 4, the register 5 divider, the first additional register 6, the third clock input 7, the second additional trigger 8, the switch 9, the memory block 10, the second and the fourth elements 2I-2ILI 11 and 12, the element EXCLUSIVE OR 13, the first element 14 delay, the first element 2I-2ILI 15, the second clock input 16, the third element 2I-2ILI 17, the element OR 18, the second element AND 1.9, trigger 20 , additional adder 21, register 22 quotient, second delay element 23, fourth and n t th clock inputs 24 and 25, output 26.

The operation cycle of the device is; n + 5 cycles, where I, 2, ..., n cycles are intended for processing the 1st (younger) 2nd, ..., nth fractional bits of the operands, (n + 1) -th, (n + 2) -th and (n + 3) -th cycles are intended for processing the whole bits of the operands (the next remainder after the shift by two bits to the high bits can have 3 whole bits), (n + 4) is the tact for representing the sign and (n + 5) th cycle is the service one for controlling the circuit. Register 1, designed to store the dividend X and the next residue 0, contains n + 7 bits. In each cycle, the operand is shifted by 2 bits towards the higher bits. The divisor H is stored in register 5, which has n + 5 bits. The unit outputs of the first second – sixth triggers of register 1 (counting from the left) are connected to the inputs of a six-bit parallel register 6, built on D-triggers. Record management in the register 6 is performed by the signal C 5, coming from input 7. At the beginning of the service cycle, the six most significant bits X or Q are written to register 6

492

and the whole cycle is stored in it. The unit outputs of the fourth, sixth, seventh, and eighth triggers of register 5 are connected to the inputs of a parallel four-bit register 8 in the same way as register 6. The write to register 8 is also controlled by the C 5 signal. therefore, in register 8, the sign and the second, third, fourth most significant bits of the divider are written in the service cycle (the divisor is assumed to be normalized, therefore the first most significant bit is not needed). The forward and inverse outputs of the sign bit () of register 8 are connected to the control inputs of the switch 9, which consists of 3 AND-OR elements. If T 0, the second, third, and fourth bits Y pass through the switch, do not change. If T, 1, they are inverted. Block 10 has 4 outputs: I1, I2, IZ and I4. The firmware of block 10 is made in accordance with the data given in the table. In view of the thunder of the d-bone, the table is shown with gaps. In the table, the outputs of register 6 are denoted by X

5 tn-ij - ni-n t

 The outputs of register B are denoted by V ,, ,, Y.,) y, and the outputs of block 10 I1 and I2 control inputs 1 and 2 of the AND-OR element. 11 The outputs OF and OF 4 of block 10 are connected to the first and second inputs of the AND-OR element 12 The element AND-OR 12 forms a character that must be assigned to the divisor. The assignment of a character is made using an EXCLUSIVE OR element. 13. If the output of element i. AND-OR 12 is a zero, a multiple of the divider passes through the element 12 without changing if is a one, a multiple of the divider is inverted. The transfer generated in adder 4 is delayed by one cycle in delay element 14. The element AND-OR 15 serves to extinguish the transfer to the lower order bit and correct the inversion multiple of the divisor in addition to assigning a minus sign to it. The AND-OR elements 17, OR 18 and AND 19, the trigger 20, the adder 21, the register 22 and the delay element 23 are a counter of the type CDA. On the codes of the elements AND-OR 17 from the inputs of the device 24 and 25 signals S3 and C4. The signal СЗ 1 in the second cycle, the signal С4 1 in the third cycle. Let the output of the element AND-IPI 12 - unit, then, if through the elements AND-OR 17 and OR 18 to the input of the adder 21, the unit passes into the second 31

The rum clock and the contents of register 22 is increased by +2. If the input to the adder 11 unit passes in the third cycle and the contents of the register 22 is increased by +4. The trigger 20, reset by the signal C5 to zero in the service cycle, remains at zero. Let now at the output of the AND-OR 12 element be zero, then if I1 at the beginning of the second clock cycle, the flip-flop 20 is transferred to one and in all clock cycles, starting from the second and to the service one, units will be input to the input of the 21. The contents of register 22 change to -2. Similarly, if, the input of the adder 21 will receive a unit in all cycles, starting with the third. The contents of register 22 change to -4.

Register 21, designed to accumulate quotient, contains n + 7 bits. In each cycle, its contents are shifted by 2 bits towards the higher bits.

The device works as follows.

Before the start of division, a normalized divider with an arbitrary sign in the additional code is written to register 5. The divider sign must be recorded in (n + 1) -m, (n + 2) -m, (n + 3) -m, (n + 4) m bars. Upon completion of the recording in the service cycle, the sign, second, third, and fourth most significant bits will be overwritten in register 8 and will remain there during the entire division operation.

In the next cycle, the dividend X is written in register 1 ,. lying within 1: g, / X /. O - r with arbitrary

sign in the additional code. In the service cycle, the sign and the five most significant bits X will be overwritten in register 6 and will be saved for the next cycle. In the third cycle, the division itself begins. At the first input of the adder 4 receives a quadruple dividend 4 x. Block 10, decoding the high-order bits of the divisible and the divider, generates the signals I1-I4. The element AND-OR 11, controlled by the signals I1 and I2, selects the desired multiple divider: O, 2y, 4y. In the AND-OR element 12, the sign of changing the sign of the multiple is formed, and with the help of element 13 the required sign is assigned a multiple of the Multiple divisor with the assigned character 494

the com enters the second input of the adder 4, and in the latter the first remainder 0 is formed. At the same time, the first bit quotient enters the counter of the type CDA.

Likewise, completes c cycles. By doing the last

the loop from exit 26 is read quotient.

Claims (1)

Formula Eteni A device for dividing numbers containing registers of the dividend, divisor and quotient, two delay elements, an adder, an EXCLUSIVE IL element, a trigger, two 2I-21 LI elements and an AND element, the output of the lower digit of the dividend connected to the first input of the And element whose output with the first information input of the adder, the output of the sum of which is connected to the shift input of the dividend register, the first clock input of the device is connected to the second input of the AND element, the output of the EXCLUSIVE OR element is connected to the second information input of the adder, the transfer output of which is connected to the input of the first delay element, the output of which is connected to the direct input of the first element AND of the first element 2I-2ILI, the inverse input of which is connected to the first input of the second element AND the first element 2I-2IL, and is the second clock input device, the output of the first element 2I-2ILI is connected to the transfer input of the adder, the output of the lower bit of the register divider is connected to the shift input of the register divider, characterized in that, in order to improve speed, two additional registers are introduced into it Istra two elements 2I-2ILI, a memory unit, a switch, an additional adder, an additional AND element and an OR element, while the outputs of the first, second, third, fourth, fifth and sixth digits of the dividend register are connected to the information input tiepBoro of the additional register the output of which is connected to the first input of the memory unit, the second address input of which is connected to the output of the switch, the first and second information inputs of which are connected respectively to the forward and inverse outputs of the first, second and the third high-order bits of the second additional register, the forward and inverse outputs of the sign bit of which are connected respectively to the first and second control inputs of the switch, the outputs of the first, second, fourth, sixth, seventh and eighth bits of the register of the divider are connected to the information the input of the second additional register, the recording resolution input of which is connected to the recording resolution input of the first additional register, with the R input of the trigger and the third clock input of the device, the outputs of the first and volts Or senior senders register divider connected. with the first inputs of the first and second elements And, respectively, of the second element, the second inputs of which are connected to the first inputs of the first and second elements And respectively of the third element 2I-2ILI and the first and second outputs of the memory unit, the third and fourth outputs of which are connected to the first inputs of the first and the second element And, respectively, the fourth element 2I-2ILI, the second inputs of which are connected respectively with an inverse and direct output The first bit of the second additional register, the output of the second element 2Y-2IL, is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to the output of the fourth element 2I-2ILI, to the second input of the second element I of the first element 2I-2IL, and to the inverse input An additional element And, the output of which is connected to the S-input of the trigger, the output of which is connected to the first input of the element OR, the second input of which is connected to the direct input of the additional element And and the output of the element 2И-2ИЛИ, the second inputs of the first and And whose elements are the fourth and fifth clock inputs of the device, the output of the sum of the additional adder is connected to the shift input of the private register and is the output of the device, the output, the register of the private is connected to the first information input of the additional adder, the second information input and transfer input connected respectively to the outputs of the OR element and the second delay element, the input of which is connected to the transfer output of the additional adder. Table continuation TCJI Tzn Tzz Tzg ni-s ni-tf iH-3 ni-2 rj L fj. one five Tn-i 7 Tt Tel nt-j n-r n-f-5 n