SU1290303A1 - Device for dividing decimal numbers - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in arithmetic devices of universal and specialized calculators that process binary-to-ten information. The purpose of the invention is to increase the speed of the device. To achieve the goal, a block of memory, a switch of divisible bits, a decimal adder are entered into the device. The calculation time of the quotient is reduced due to the fact that, having the results of the prepared intermediate sums available, the quotient calculation process is an operation of adding to each other those intermediate sums, the numerators of which are divisible, and the number of additions is equal to the number of decimal places. divisible regardless of the required accuracy of the calculation of the quotient, i.e. for t-bit divisible, the number of addition operations will be m regardless of the size of the quotient. The number of private register tetrads is reduced by 1 compared with the number of input tetrads of the adder. The decimal adder consists of a set of tetrads by the number of decimal bits of intermediate amounts called from the memory block, with the highest tetrad of the second information inputs of the adder connected to the logical zero bus of the device, which ensures the order of addition of intermediate amounts stored in it in the form of matrices. 1 il. with (L; about about with about 00

Description

1 .1290303

Invention refers to compute

technical equipment, and can be used in the arithmetic devices of universals-1yk and specialized calculators that process binary-tenth information.

The purpose of the invention is to increase speed.

. The drawing shows the functional diagram of the device for dividing decimal numbers.

The device circuit contains a register I divisible, a register 2 dividers, a register 3 private, a decimal adder 4, a memory block 5, a switch 6, a distributor 7 pulses, a generator 8 clock pulses, an input 9 of the logical zero of the device. The number of tetrads of register 3 is reduced by 1

Compared with the number of input tetrads of the adder 4, the Decimal adder 4 consists of a set of tetrads by the number of decimal digits of the intermediate sums called from memory block 5 with the highest tetrad 2 informational inputs of adder 4 connected to the input 9 of the device. In memory block 5, information is stored on intermediate amounts in the form of a matrix of the following form:

Where

in the system 8., 4, 2, 1.

Addressing the address of the corresponding row of the matrix provides information from the output of register 2 of the divider, and calling the corresponding subtotals from the selected row provides information from the output of the torus 6, and the size of the results of the subtotals is determined by the size of the particular and must exceed it.

The distributor 7 pulses are composed of a p-rar counter with the input of the blocking of the count and the identification circuit of the beginning and end of the calculations, where n is the number of decimal digits of the dividend.

The device works as follows,.

five

0

five

0

five

In the initial state, the values of the operands are entered in registers 1 and 2, and register 3 is zero. At the beginning of the computation cycle, the generator 8 is started and the distributor 7 generates signals that control the dividend by the lower bits and the resolution signal by reading the intermediate sums from the memory block 5. As a result, the Gth intermediate sum arriving at the 1st information inputs of the adder 4 is read. Adder 4, having received the 1st intermediate sum at the 1st inputs, and the contents of register 3, at the 2nd informational inputs. provides their decimal addition, and the result obtained by the signal from the output of the distributor 7 is transferred to the register 3, and the switch 6 gives the next bit of the dividend, the value of which is the address for reading the 2 intermediate sum, which is summed up with the contents of the register 3 The result is again transferred to the private register for storage until the next calculation cycle. All subsequent calculation cycles are repeated in the same order.

At the end of the computation cycle, the private distributor 7 generates signals that prohibit access to memory block 5 and snore the result of the private.

Claims (1)

Formula invented and A device for dividing decimal numbers containing registers of the dividend, divider and quotient, clock pulse generator, pulse distributor, switch, the clock pulse generator output connected to the pulse distributor start input, the first output of the i-ro bit (where i 1 , 2, ..., p, n is the number of decimal digits of the dividend) which is connected to the i-th control input of the switch, characterized in that in order to improve speed, a memory block and a declaring adder are entered into it, and the output i-th tetrade divisible register connected to the information input of the co-opa- tor, the output of which is connected to the first address input of the memory unit, vto3129D303 the address address input of which is connected to the divider register output, the second output of the pulse distributor is connected to the readout input of the memory block, the output of which 5 is connected to the first information input of the decimal adder, the highest tetrad of the second information input of which is connected to the input of the logical zero device - ABOUT The third output of the pulse distributor is connected to the input of the write resolution of the private register, the output of which is connected to the second information input of the (t − 1) –th junior tetrads of the decimal adder, where t is the size of the decimator adder whose older tetrads are connected to the information entry of a private register. 3