SU1425665A1 - Digital logarithmic converter - Google Patents

Abstract

The invention relates to computing, technology and can be used in computer arithmetic devices and digital information processing systems. The aim of the invention is to expand the scope of use by allowing the function to be calculated from an arbitrary integer argument. The digital logarithmic converter contains input 1 and output 10 registers, register 5 of the normalized argument, high-order block 3, encoder 2, shifter 4, two blocks 6, 7 of memory, block 8 dividing, summator 9 and pulse distributor 11. The converter selects the characteristic (the whole part of the result) of the whole binary number and forms from it the normalized value of the argument from which the mantissa (Fractional part) of the result is calculated. 2 Il. c (lgo sp o about: a cd

Description

The invention relates to digital computing and can be used in the construction of specialized calculators, information and measurement systems, digital filters, and hybrid functional converters.

 The aim of the invention is to expand the scope of use by allowing the function to be calculated from an arbitrary integer argument.

FIG. 1 shows a functional: digital logarithmic converter circuit; in fig. 2 - time diagram of his work.

The digital logarithmic converter (Fig. 1) contains an input register 1, an encoder 2, a block 3 of selection I, no higher order, a shift device 4, j a register of 5 normalized argument I, the first 6 and second 7 memory blocks, I block 8 division, adder 9, the output register 10, the distributor 11 pulse 1 ow.

I Digital logarithmic converter handles whole binary I numbers and function computation, x I performs by the algorithm

I,

| Z lo8 x logJ2 U) K + logiU; one,,

: Z, p K log Uo-f21ogJ.

(one)

Z ,, K + A, Z s

; A 1st

I. + 2

t. °

log.J; A., -2Uc, 1st ,, 1,

where Zr, p is the approximate value of the result; K is a characteristic of the number x; And - the normalized value

argument;

HO is the reference value of the argument U. A digital logarithmic converter that implements algorithm (1) works as follows.

The converter starts the calculation of the logarithmic function x from the signal entering the distributor 11 pulses through its input. The distributor 1t pulses generates a sequence of control signals, rfo the signal from the first 1 offset of the distributor 11 pulses, the value of the argument x is fed to the Digital Logarithmic Converter via the information input

,

five

0 5

0

five

0

second register 1. The signal from the second output of the distributor 11 pulses of arguments in the form of a whole positive integer binary number is fed to the input of the high-order block 3, at the output of which the signal is output in the bit position of the highest X code unit. This signal is received to the input of the encoder 2, the output of which is the binary code of the characteristic K of the number X. The characteristic K is the sequence number

. the bit containing the leading unit of the argument x, starting the count with zero to the side of the higher bits from it. The characteristic K as an integer part of the result goes to 1 most significant bits of the output register 10. The code of the number K is fed to the input of the shifter 4, to another input of which comes the code of the number x, which is shifted to the K bits to the right

° (in the direction of the younger bits). Since the number X 2 U; 1 U 2, then the output of the shifter 4 produces a normalized argument U, the code of which is written to the register 5 of the normalized argument. The code of the characteristic K in the output register 10 and the normalized argument U in the register 5 of the normalized argument is written according to the signal generated at the third output of the distributor 11 pulses. .

The signal from the fourth output of the distributor 11 pulses arriving at the control input of the dividing unit 8 enters the last divider and -n

2

1 °.

-. Q

second output register 5

normalized argument and value A from the second memory block 7 according to the address generated at the first output of register 5. At the output of dividing unit 8, the value is generated

l / and + io

Ag / ---. By the signal from the second output

the distributor 11 pulses, delivered to the control input of the adder 9, the last received UU + Uo

2

respectively from the outputs of the first

block 6 of memory and block 8 division. . In the code adder 9 is generated

ranks A, (0 Io + log 1) A, / - value W.,

2 logl Jj ;; jf..logu

W: ° 8 and. +

recorded on

3142

in p the lower bits of the output register 10 according to the signal generated at the sixth output of the distributor 11 pulses.

In the p-bit output register 10., in accordance with algorithm (1), the result of Z log x, which is a positive binary number with a fixed comma, with the integral part (characteristic K) occupies 1 most significant bits, the fractional part is placed in p n - 1 minor bits. The result of Z log X is fed to the output of the digital logarithmic converter by a signal from the seventh output of the distributor 11 pulses, and at the eighth output of the distributor 11 pulses a signal is generated indicating that the result calculation has been completed.

Claims (1)

Formula of the invention A digital logarithmic converter containing a register of a normalized argument, a first memory block, a division block, an adder and an output register, the output of the MSB group connected to the address input of the first memory block, the output of which is connected to the input of the first one operand the rand of which is connected to the output of the block division, the input of which divider is connected to the output of the bits of the lower group of the register of the normalized argument, the output of the adder is connected to the inputs of the younger group of the bits of information the input register of the output register, characterized in that, in order to expand the scope of application due to the possibility of calculating a function from an arbitrary integer 0 five 0 665 the argument, an input register, a higher-order allocation block, an encoder, a shifter, a second memory block, and a T1 allocator are entered into it, and the input argument of the converter is connected to the information input of the input register, the output of which is connected to the information input of the SD and the information input of the high-order block of output, the output of which is connected to the information input of the encoder, the output of which is connected to the input of the higher-order bits of the information input of the code register and the control input of the shift I ate, whose output is connected to the invariant formatsionntm Normalization input register. argument, the output of the high-order group of which is connected to the address input of the second memory block, the output of which is connected to the input of the divisible division block, the converter start input is connected to the pulse distributor start input, the first and second outputs of which are connected to the inputs of the recording resolution and resolution, respectively read input register, third output 0, the pulse distributor is connected to the write enable input to the register of the normalized argument and the write enable input to the higher bits of the decoder register, the codes from the fourth to the eighth pulse distributor are connected respectively to c. the control input of the division unit, the control input of the adder, the write enable input to the lower bits of the output register, the enable input of the output register, and the output of the calculation end of the converter, whose information output is connected to the output of the output register. five five rx "o Jt "V4  “O. ro "Q 5s