SU1087990A1 - Device for raising to power - Google Patents

Abstract

A DEVICE FOR CONDUCTING TO A DEGREE containing a switchboard, K computing blocks, each of which contains a switch, a quadrant torus, a multiplier (where, m is an exponent), and in each computing block the output of the quadrant is connected to the first information input of the multiplier and the first information input a commutator characterized by; that, in order to increase speed, a NOT element is entered into the device, and a degree base register, a degree indicator register and a result register are entered into each computing unit, the first information input of the device’s switch is connected to the information input of the degree register and the base input of the power level; the information input of the device switch is connected to the bus of the logical unit of the device, the input of the device degree indicator is connected to the input of the element NOT that first controls the input ohm device switch and information input register of the exponent of the first computing unit, the output of the element is not connected to the second control input of the device switch, clock inputs of the base register of the degree, result register and exponent register Each computing unit is connected to the clock input of the device, register output the base of the degree of the i-th computing unit (, K) is connected to the second information input of the multiplier of the 1st computing unit, the output of the multiplier of the 1st computing unit unit is connected to the first information input of the switch of the i-th computing unit, the output of the switch device is connected to the information input of the register of the result of the first computing unit, the output of the register of the result of the i-th computing unit is connected to the input (the formation input of the quadrant of this computing unit, output the base register of the degree of the i-th computing unit is connected to the information input of the base-degree register (i-fl) -ro of the computing block, the output of the switch of the i-th computing block is inen with the information input of the register of the result (i + l) -ro of the computational oo block, the forward and inverse outputs of the higher bit of the register are shown from the jar of the i-ro computer of the computing unit connected to the first and BTOfftjM control inputs of the i-ro switch of the computing unit , the outputs (Ki) -x of the lower bits of the register of the exponent of the i-th computing unit are connected respectively to the (K-1) th high-order bits of the register of the exponent of the (i + l) -ro computational block, the output of the switch of the last computing unit as is the output device.

Description

The invention relates to computing and can be used in high-performance digital information processing devices for computing functions. ..

A device for calculating exponential functions for N is known, which contains a control unit, a control unit, a summation unit, an adder, an Element OR, t-1 computational codes, each of which contains a multiplier, an AND element, an OR element, and a summation block that contains a register, an adder and switch Cl3.,

The closest to the present invention is a device for raising to a power containing a switch, K computing blocks, each of which contains a switch, a quarantine, a multiplier (where, t is an exponent), and each computing block is connected to the output of the quadrator switch lll.

A disadvantage of the known devices is low speed.

The purpose of the invention is to increase the speed of the device.

The goal is achieved by the fact that a device for raising to a power containing a switch, K computing blocks each of which contains a switch, a quad, a multiplier (where K teg-jir, is an exponent), and in each computing block the output of the quad is connected to the first the information input of the multiplier and with the first information input of the switch, the element is entered, and in each computational, the block is entered the base register of the degree, the register of the exponent and the result register, with the first information input The device switchboard is connected to the 7th input of the base register of the power and the device’s base input, the second information input of the device switch is connected to the bus of the logical unit of the device, the device’s power indicator input is connected to the input of the HE element, the first governing input of the device switch and the registrar's information input the exponent of the first computing unit, the output of the element is NOT connected to the second control input of the switchboard device, the clock inputs of the base register Step audio, result register exponent register kazhogo computing unit connected to the clock input of device yield

base register

computing unit, K) is connected to the second information input of the multiplier, i-th computing unit, the multiplier output of the i-th computing unit is connected to the first information input of the switch 5 of the 1st computing unit, the output of the device switch with the information input of the result register of the first computing unit , the output of the register of the result 0 of the i-th computing unit is connected to the information input of the quadrant of this computing unit, the output register of the base of the degree of the i-th computing unit is connected to in5 by the formational input of the base register of the degree (1 + 1) -th calculator. the output unit, the output of the i-ro switchboard of the computing unit is connected to the information input of the result register (i + l) -ro of the computing unit, the direct and inverse outputs of the most significant bit of the indicator register. the degrees of the i-th computing block are connected respectively to the first and second control inputs of the switch of the 1st computing block, the outputs (Ki) -x of the least significant bits of the register of the exponent of the i-th computing block are connected to the (K-1) -m elders

0 bits of the register of the exponent of the (1 + 1) -th computing unit, the switch output of the last computing unit is the output of the device.

5 The drawing shows a block diagram of the proposed device. . The device contains the element 1.NE, switch 2, K computing units 3, each of which contains

Q register 4 bases of degree, register 5 of result, register b of exponent b, quad 7, multiplier 8, switch 9, input 10 of exponent of device, input 11 base. ki degree devices, clock

 device input 12, bus 13 logical unit of the device.

The number of computational units

3 is determined by the formula m,

.those. To a smaller integer value of the expression 8о ,, т.

The device for exponentiation uses a binary method of reducing the number of multiplications. In the exponent recorded in

5 of the binary number system, the extreme left unit is defined. When reading numbers consecutively, to the left of this unit, the following operations are performed: if the next digit is zero,

About the result of the previous operation

squared; if the next digit is one, then the previous result is squared, and then multiplied by the base of the grade 5. For the initial result takes with the foundation of the degree. The device works as follows. In the first cycle, the basis of the first computational unit 3 is written to the base 4, the power of the degree, the power exponent without the first discharge is written to the B register. in the junior category (first level of the exponent zero). The transfer of the necessary information to the result register 5 is performed by the switch 2, controlled by the first digit of the exponent. On quad 7, the number recorded in the result register 5 is raised to the square. The result of the squaring goes to multiply B, where it is multiplied to the base of the degree. The results from the multiplier and quadrant are received respectively on the first and second information inputs of the switch 9 and, depending on the value of the second bit of the exponent, the output of the switch 9 receives the result of multiplication (the second bit of the exponent is equal to one) or the result of squaring the second d exponent is zero).

/ ft

10 In the second cycle, the calculation result of the first computational unit 3 is recorded in the second, the information from the outputs of the switch 9 is written to the register 5, the transfer of the base degree value to the base 4 register of the degree. recording the exponent in the register 6 exponent. At the same time, new elements of the processing array are written to the first computational unit 3. In each computing unit 3, one iteration of the exponentiation algorithm is performed. The exponentiation operation is performed when the operands pass through all computational units 3. The proposed device operates according to the conveyor principle. Its speed is determined by the execution time of one iteration, i.e. tact of the conveyor. This time is determined by the formula G, tp2 + t Kg + t ,,, where tpj is the recording time of the infirmation in the register; delays of information, respectively, quad, switch and multiplier. Thus, the proposed device allows to increase the speed, and especially it is advantageous to use it when processing a large amount of data.

Claims (1)

A DEVICE FOR DEGREEING TO A DEGREE containing a commutator, K computing units, each of which contains a commutator, a quadrator, a multiplier (where K = toQ- ₂ m, hl is a degree indicator), and in each computing unit the quadrator output is connected to the first information input of the multiplier and with the first information input of the switch, characterized in that; that, in order to improve performance, the element NOT is introduced into the device, and the degree base register, the degree indicator register, and the result register are entered into each computing unit, the first information input of the device switch being connected to the information input of the degree base register and the input of the device degree base, the second the information input of the device switch is connected to the bus of the logical unit of the device, the input of the exponent of the device is connected to the input of the element NOT, the first control input comm device and information input of the register of the exponent of the degree of the first computing unit, the output of the element is NOT connected to the second control input of the device switch, the inputs of the register of the degree base, the register of the result and the register of the exponent of each computing unit are connected to the clock input of the device, the output of the base register degree of the i-th computing unit (i = l, K) is connected to the second information input of the multiplier of the i-th computing unit, the output of the multiplier of the 1st computing unit with connected to the first information input of the i-ro switch of the computing unit, the output of the switch-device is connected to the information input of the result register of the first computing unit, the output of the result register of the i-th output g of the computing unit is connected to the information input of the quadrator of this computing unit, the output of the base register degree of the i-th computing unit is connected to the information input of the base register of the degree of (i + l) -ro computing unit, the output of the switch of the i-th computing unit is connected to the information by the ion input of the result register (i + l) -ro of the computing unit, the direct and inverse outputs of the highest order of the register of the exponent of the degree of the i-th computing unit are connected respectively to the first and second control inputs of the i-ro switch of the computing unit, outputs (Ki) -x are junior the bits of the register of the exponent of the i-th computing unit are connected respectively to the ((-ϊ) -μη senior bits of the register of the exponent of the (i + l) -ro computing unit, the output of the switch of the last computing unit is the output of the devices a.