SU1179326A1 - Pipeline device for calculating value of function y=sin(p/4x) - Google Patents

Abstract

A CONVEYOR DEVICE FOR CALCULATING FUNCTIONS lj 5ini-X containing an input register, two memory blocks, four intermediate registers, two adders, an output register whose information input is connected to the output of the first adder, the output of the higher bits of the input register is connected to the address input of the first memory block TI and the information input of the first intermediate register, the output of which is connected to the address input of the second memory block, the output of the second adder is connected to the information input of the third intermediate register, characterized in that, in order to simplify the device, it contains a k-vadrator, a block: synchronization and a shifter, with the output of the 1st bit of the input register i 1,2, ... Ij where n is the width of the argument connected to the first input (i + 4) -ro bit of the second adder, the second input of (i + 4) -ro bit of which is connected to the code of the first memory block, and the output of (i + 4) -ro bit of the second adder is connected to the input of the corresponding bit Yes, the third intermediate register, the output of which through the quad is connected to the information input of the fourth intermediate the register, the output of which is connected to the information input of the shifter, the outputs of the two high-order bits of the second intermediate register are connected to the control inputs of the shifter, the inverse output of which is connected to the first input of the first adder, the second input of which is connected to the output of the second memory block, the synchronization block contains the element I, the trigger, the generator of pulses and the shift register, the information and control inputs of which are connected respectively to the direct output of the trigger and the inverse output of the gene pulse generator, the direct output of which is connected to the trigger synchronization input, information input @ is connected to the output of the element I, the first and second inputs of which are connected to the inverse output of the trigger and the start input of the device, respectively, the reset input of which is connected to the installation inputs the trigger and shift register, the output of the third bit of which is connected to the synchronization input of the input register, the synchronization input of the first and third intermediate registers are connected to the output of the fifth bit register a shift, the output of the seventh bit

Description

which is connected to the synchronization inputs of the second and fourth intermediate registers, the output of the ninth 1179326 shift register bit is connected to the synchronization input of the output register.

The invention relates to the field of computing and is intended for use in universal and specialized computing devices when processing large data arrays.

The aim of the invention is to simplify the device.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - synchronic block; in fig. 3 - time diagrams of the device.

The device (Fig. 1) contains an input register 1, a memory block 2, an adder 3, intermediate registers 4 and 5, a quadrant 6, intermediate registers 7 and 8, a shifter 9, a memory block 10, an adder 11, an output register 12, a block synchronization 13 with outputs 14-19 and inputs 20. and 21.

The synchronization unit 13 (FIG. 2) contains a pulse generator 22, an AND 23 element, a trigger 24 and a shift register 25.

Kvadrator 6 can be performed in various ways, o must have sufficient speed. In particular, a fast multiplier can be used as a quadrant.

Intermediate registers 4, 5 and 7, 8 are designed for. short-term storage of the results of intermediate views and to provide a conveyor processing method. At the same time, register 4 has a width of 11 + 4 (with a register size of 1 and 12 equal to I), register 7 has a width of h +6, and registers 5 and 8 have a size of K.

Calculation of the function function nsglnf xl

from the argument X (О X i 1) is made on the basis of the segment approximation method by the expression Ij А + W (Х + В), where the constants are А,

8.1 is chosen from the condition of minimizing absolute error. Here, the coefficient W is chosen equal to the power of the number two. For / function

lj sin (- | -x coefficient A is eI,

with positive and coefficient B negative, regardless of the number of partitions of the interval of change of the argument into segments. The coefficient W takes in-dependence on the two leading bits of the argument, four values: - 0.03125, - 0.0625, - 0.125, - 0.25.

The range of the variation of the argument o, l is divided into intervals, the number of which is determined by the required accuracy, the interval limits being expressed by the higher binary bits of the argument.

At different intervals, the constants A. and B have different meanings. The constants B are stored in memory block 2, and the constants A are stored in memory block 10. Each memory block is addressed by the most significant bits of the argument, which determine in which interval the argument is located. The size of the memory blocks 2 and 10 is determined by the required accuracy of the calculation of the function. For intervals corresponding to the range of variation of the argument 0.1 /, the coefficients A and B correspond to the best uniform approximation.

  / If functions, (4: i

yes Ij - A - 0.03125), in the range 1/4, 1/2 - in A - 0.0625 (U + B), in the range 1/2, 3/4 - jj А 0, 125 (x + B ), in the range of 3/4, ijij-A - 0.25 (x + B).

The device works as follows.

Before processing the array of numbers, the Reset signal (Fig. 3q) is sent to the input 21 of the Reset of the Synchronization Block 13, which triggers the 24 and the shift register 25 to the initial state. After the arrival of the signal 20 Start (Fig. 3S), the element And 23 allows the passage of information from the inverse output of the trigger 24 to its information input. Trigger 24 performs a frequency division of the generator of 22 clock pulses into two (Fig. 3b). On the leading edge of the pulses from the inverted output of the generator 22, the information from the output of the trigger 24 is entered into the shift register 25 and with each new pulse shifts to the right. The output of the first bit of the shift register 25. controls the reading of numbers from external memory blocks (Fig. 3q), the output of the third bit controls the shift of the input register 1 to the output 15 (Fig. 3 e). The output of the fifth bit of the register 25 controls the offset of the numbers in registers 4 and 5 (FIG. 3 k) on output 16. The output of the seventh bit of the register 25 controls the offset of numbers in registers 7 and 8 (FIG. 3, L) on the output 17 of the synchronization unit 13. The output of the ninth bit of the register 25 controls the input of numbers to the output register 12 (FIG. 3 I) on the output 18 of the block 13. The output of the eleventh bit of the register 25 controls the writing of the output number to the external memory blocks on the output 19, block 13. The output of the even bits of the shift register 25 is not used. The structure of the synchronization unit 13 takes into account the inertia of the conveyor and, after removing the signal, the Start correctly completes the development of the numbers previously accepted for processing. In the first cycle of the device operation, the argument X enters in register 1 ,. From the output of register 1, the value of the argument arrives at the adder 3 with a shift of 4 bits to the right. Simultaneously, a constant B is selected from the memory block 2 at the address indicated by the most significant bits of the argument X,, and also fed to the adder 3. In the adder 3, the sum X, + B, is generated. In the second cycle, the value X, + B, is written to register 4 and squared to 6. In the same cycle, the value K of the leading bits of the argument x is written to register 5, and the register 1 receives the next value of the argument X. In the third cycle the value (x, + B,) is written to the register 7 and through the shifter 9 enters the input of the adder 11 without shifting or shifted by one, two or three bits to the right. At the same time, the value of K of the higher bits of the argument Xi, which is the address of the constant A ,, stored in block 10, is rewritten from register 5 to register 8. The value of the two most significant bits of register 8 is also fed to the shift control inputs 9 and controlled by the shift values (B,) Constant A, comes from memory block 10 to the second input of adder 11, where the sum A, -W, (x, + B,) is generated, since W is always negative, then adder 11 actually works on subtraction. In the same clock cycle, register 4 records the value, and register 5, the value of the k higher bits of the argument Vg. Register 1 writes the next XsB number to the fourth cycle; register 12 records the value of c A, + V, {) C, + B,) . is an approximation of t. | jB point X -X ,. registers 4, 5 and 7, 8 are written by the intermediate calculations hell with arguments x2 and xj, and in register 1 a new number x4 is written

m sisiim

Record

, Siip18aiiie FIG. 2

P

l

L-PL p p gpr p p p p p rLn-rTrLjnjTJTjTLTLriJT-rL

JL J LJI-L

-t t t -t t

 . -t

FIG. J

Claims (1)

CONVEYOR DEVICE TO CALCULATE THE FUNCTION lj = 5in ^ xj, which contains an input register, two memory blocks, four intermediate registers, two adders, an output register, the information input of which is connected to the output of the first adder, the high-order output of the input register is connected to the address input of the first memory block and information the input of the first intermediate register, the output of which is connected to the address input of the second memory block, the output of the second adder is connected to the information input of the third intermediate register, characterized in that, for the purpose forgiveness device, it comprises a squarer unit 'synchronization and wherein the shifter output ί -th bit input register ί = 1.2, P ₃ ..., and where - the bit argument, coupled to the first input of G' + 4) -ro second discharge an adder, the second input of (i + 4) -ro discharge of which is connected to the output of the first memory block, and the output of the (1 + 4) -th discharge of the second adder is connected to the input of the corresponding discharge of the third intermediate register, the output of which is connected through the quadrator to the information input of the fourth intermediate register, the output of which is connected to information input of the shifter, the outputs of the two high-order bits of the second intermediate register are connected to the control inputs of the shifter, g the inverse output of which is connected to the first input of the first adder, the second input of which is connected to the output of the second memory block, and the synchronization block contains an element And, -trigger, pulse generator and a shift register, the information and control inputs of which are connected respectively to the direct output of the trigger and the inverse output of the pulse generator, the direct output of which is connected to a trigger synchronization signal, the information input of which is connected to the output of the And element, the first and second inputs of which are connected to the inverse trigger output and the device start input, respectively, the reset input of which is connected to the trigger and shift register input inputs, the third discharge of which is connected to the input synchronization input register, the synchronization input of the first and third intermediate registers are connected to the output of the fifth digit of the shift register, the output of the seventh digit of which is connected to the sync inputs tions intermediate the second and fourth registers, the output of the ninth discharge shift register connected to the input of output register synchronization.