SU783791A1 - Polynominal multiplying device - Google Patents

Description

(54) DEVICE FOR THE MULTIPLICATION OF MULTI-MEMBERS

The invention relates to the field of computing and can be applied, for example, in specialized computing devices to find the product of operands represented by polynomials. Computing devices are known for generating coefficients of a polynomial. |. equal to the product of many of Rlaine 5. on a multitude of S ВХ 11. These devices are universal digital computers, and, in addition to the number of polynomial participants, the devices are performed by implementing the corresponding program. However, the computational method has inherent drawbacks such as low speed and relatively large hardware costs for the implementation of a universal digital computer with a relatively low efficiency of their use. The closest to the claimed is a device containing n + 1 registers of coefficients of the first polynomial, n-I registers of the coefficients of the second mbglochlen and n + 1 accumulating adders having a shift circuit, the result registers the unit of analysis of bits of operands, the shift block, the switch and control unit 2. This device has no disadvantages inherent in devices 1, since the multiplication of polynomials is implemented in hardware. However, the known device also has a low speed, which can be determined by the formula Ti (n + l) p (t + tc | i) n - degree of multiplied polynomials p - bit A; and the shift time tt is the summation time. The purpose of the invention is to increase the speed of the known device. bits accumulating adders, and the distributor of signals connected to

control inputs of all registers and accumulating adders. The outputs of each i-ro register, ..., p + 1) through; are connected to the information inputs of i-TO, i + l-ro, i + 2, ... ,, n + l-th accumulating adder, input the bus of each i-ro coefficient of the first and second polynomials of the device is connected to the first control input of the corresponding register and to the control input of i-ro, i-tl-ro, ..,, n + l-th accumulating adder, clocking bus connected to the second control inputs of the accumulative totalizers and the distributor, and the output busses of the device are connected to the outputs of the degMfrators.

Figure 1 shows a block diagram of a device for multiplying polynomials; figure 2 shows the implementation of the decoder.

The device consists of (nt-1) bit registers Ij - lj, coefficients of the first polynomial, (n + 1) bit registers 2-t - 2n-n coefficients of the second polynomial, (n + 1) accumulating cyMi jators 3 -, (ri +1) decoders 4 - 4 h, distributor 5 signals, input bus coefficients of the first polynomial 6-1 and the second polynomial 7i - 7f |. , output tires 8 - and clocking bus 9.

Registers 1 and 2 possess the properties of multi-input reversible counters “Each i-th accumulating cyNiMaTor 3, .., n + 1) contain. bits, where is the function of rounding to a larger integer. The output of the j-ro bit, ..., p) of the signal distributor 5 is connected to the input j + 1-th bit of each register. The output of the j-ro bit of the 1st register 1 and 2 is supplied to the input of the {3 + .og,) th bit (, ..., n + l) m-ro of the accumulating adder. Decoder 4 is a decoder of the second kind and -can be implemented in the form of a combinational circuit containing logic elements associated with the drive and inverse outputs of the first three bits of the accumulating adder 3 in accordance with the switching-fi a system ( .a, jaij V a, j, a), fl ai (a, a.),

where the argument indices correspond to the numbers of the digits of the adder 3, and the function indices to the numbers of the outputs of the descriptor 4.

An example of the implementation of the decoder 4 on the elements AND 10 and OR 11 is shown in figure 2. Calad i-hot bus 6 is connected to the control input of the i-ro register 1 and to the reception circuits of the kr register 2 code (, ..., n-i + 2) on (l + kl) -a accumulating adder 3. - in a similar way 1- input bus

7cw with control input of 1st register 2 and with reception circuits of k-ro register 1 code (k-1, .. ,, n-i + 2) on

The (i + k-l) th accumulating adder 3. The clock bus 8 is connected to the control inputs of the accumulating adders 3 and the distributor of 5 signals.

The device works as follows

In the initial state, in registers 0 1 and 2 and in adders 3, zeros are written.

8, each qM calculation cycle at the output of the signal distributor, the unit is q + 1 bit (the first bits are the older ones everywhere). In the first cycle q-ro, for each i-th input bus b, the digit of the coefficient Aj,. having a weight of 2 which controls the reception of the code of the distributor 5 to the 1st register 1 and

Q. Reception of k-ro register code 2 on

{i + k-l) -th cytviMaTOp 3 as follows.

If the digit q-ro bit A -, .. is equal to one, then in the qi-1-th bit of the i-ro register 1, one is added, and on {i + kl) -th adder 3, the direct code k is issued ro register 2, if this number is minus one, then one of the q + 1 th bits of register 1 is subtracted, and the specified totalizers 3

0, an additional code of the corresponding registers 2 is issued, if the digit is zero, then the contents of register 1 does not change, and the code of the indicated registers 2 does not change to the corresponding sum.

S 3 is not output, the second digit of the q-ro cycle of the q-ro digit of the coefficient B; .1, 1 the tracking weight and the input to the 1st input bus 7, in a similar way controls the addition

d (by subtracting) the unit in q + 1-th bit of register 2 and issuing the codes k-x of registers 1 to the (i-l-k-l) -th subscriber 3.

As a result of the analysis of the three most significant bits of the 1st accumulating adder 3, the i-th decoder 4 forms the next digit of the i-1-th coefficient of the polynomial, having a weight of 2P and 1 according to the following rule. The number of the result is plus one if the contents of the three most significant bits of the accumulator of the last adder 3 are equal to 001 or 01.0, minus one - if the contents of the three most significant bits equals 110 or 101, zero - in other cases. The final result figures

5 formulated decrypted 4, arrive on the weekend tires.

In the third cycle, the signal in the clock bus 9 is shifted by -0 one bit of unit in the distributor of 5 signals and left shift by one bit of the content of accumulating adders 3, and the content of the third bit of each accumulating 5 cyst during shift is not only in the second bit, but also in the first bit. To calculate the coefficients with an accuracy of p of the polynomial S, the bits of the order of a comma must perform Bogj (n + 1) + 2 + p computation cycles. Consider the work of the computing device in the following example. Let it be necessary to calculate the first three coefficients of the polynomial obtained as a result of multiplying the polynomials Ao + A X + AjX and BO + B, X + BX where, 1111; , 1101; 1111, 1111; , 1111; , 1001. For these coefficient values, the calculation process is illustrated by a table of device register states. Let us comment on the table how the device works, for example, in the third calculation cycle. Before the start of the cycle, in each of the LJ, 112 and Ij registers there are 11, in registers 2, 2 and 2 o, the numbers 11.11 and 10 are recorded, in the accumulating adders 3, 3tj and 35 there are numbers 11001000, and UNLA and 0011000000 respectively . In the first cycle of the third calculation cycle, the third digits of the registers If, 1st, and 1 are entered into the third digits of the coefficients Ad, A, and 1, O, and i Minus the unit received on bus 6 controls the order of the additional content code of register 2, additionally with a minus sign for accumulating adder 3 /, additional register content code 2, taken with a minus sign, for accumulating adder 3 and additional register content code 2, taken with minus sign, for accumulating adder. Since there is zero in bus G, outputting the contents of register 2 to the accumulator mat 3jj and the content of register 2; on accumulation adder 3 does not occur. The unit in bus b ™ controls the output of whose contents of register 2 to accumulator 3 ,. In the second cycle of the third cycle, the third digits of registers 2, 2g and 2 are entered into the third digits of the coefficients Vf, BI and Bij (1.1 and 0). The unit in the bus 7 controls the output of the contents of register 1 to accumulation of adder 3, the contents of register 1 to accumulating adder 3 and the contents of IT register, to accumulating adder Zo. The unit in the bus IQ controls the output of the register 1 / to accumulating adder 3 (and the register Ij to the accumulating adder. Since there is zero in bus 7p, the output of the register 1 to the accumulating adder 3 does not occur. After adding these codes, the decoders 4, 4, j and 4, analyzing the three highest bits of accumulating adders 3, 3n and 3g, respectively, formulate the third digits of the coefficients C, C and C (0.1 and 1), which are fed to the output tires 8. Then, by a signal in the clock bus 9 there is a shift to the right Numbers in the signal distributor 5 and left shift the contents of accumulative adders 3, 3 and 3. To get a result with a precision of Kz to five digits after the second, the described calculation cycle must be repeated Bog, j (n-4) times As B / 1THE from example, This device allows calculating the values of n + 1 coefficients of the polynomial Cf, equal to the product of the polynomial AKH by the polynomial with exact digits after the comma for each time up to the time T5; (water, () + 2 + р) (. It is possible to receive byte p, 5tj, then this device exceeds the speed known in - 7. () p TO. 5 (reogf {«-iap) For example, when the resolution is wide, this device allows calculating the coefficients of a 3rd degree polynomial 2.14 times (faster than the known, 7th degree - 4.15 times faster, 15th degree - 9.6 times faster.

Claims (2)

1. Author's certificate of the USSR W 451088, cl. G About F 15/20, 1974. 2. USSR author's certificate No. 495663, cl. G 06 F 7/38, 1975 (prototype).