SU875461A1 - Storage device - Google Patents

Description

(54) STORAGE DEVICE

I

The invention relates to computing technology and can be used in computing data processing systems.

A register is known that contains a trigger chain and an output valve for storing and transmitting information tl.

The disadvantages of the known device | "is the low reliability of the stored information and the inability to detect errors that occur during storage due to the zero error-detecting ability of the c codes. the classical binary number system, by which information is presented in per and country; x.

Closest to the proposed technical entity is a memory device that contains 20, a trigger and an outlet valve C2.

The disadvantage of this register is that the reliability of the stored information is mgsha and that it is impossible to find out. no mistake.

The purpose of the invention is to expand the field of application of the device due to the normalization of the binary code FibOnich chi.30

This goal is achieved by the fact that a control unit and: an element AND, whose outputs are, with the device outputs, are entered into a memory device containing a drive. code master, control unit, trigger and an OR element, the first group of inputs of which is connected to informational inputs of the device, the second group of inputs of the OR element is connected to the first output of the control unit, the second output of which is connected to the first group of inputs the element inputs of the OR or connected to the first group of outputs of the code converter, the second group of outputs of which is connected to the first group of inputs of the control unit, the second input of the control unit connects to the first output of the trigger, the outputs of the accumulator co dineny the first group of input transducer codes the second input of which is connected to vtorm trigger output, the first input group of AND is connected to the outputs of the accumulator, a second input group connected to the third output of the control unit, the fourth and fifth outputs to; torogo connected to the inputs of the flip-flop.

The drawing shows the functional scheme of the device.

The device contains a control unit 1, an OR element 2, a drive 3, a 4-code converter, a control block 5, an And b element, a trigger 7.

Converter 4 code is made on 7 elements And 8-14, three elements NOT 15-17 and a multi-input element And 18.

Unit 5 of the control contains a multi-input element And 19 and the element OR 20. The device works as follows.

On a signal from control unit 1, all triggers of accumulator 3 are zeroed. On the next signal of block 1, the binary fibonacci code is written to the drive 3 via the element OR 2. The next signal of the block 1, the trigger 7, which is in the zero state, is transferred to the single state, the And 8 element is opened and the device is transferred to the normalization mode, in which the binary Fibonacci code is brought to normal form, in which code can not be immediately two units. The principle of operation of the 4-converter is the sequential viewing of the binary code, starting with the higher bits. If there are units in two adjacent bits, a convolution operation is performed, the form of which is

01011 - unnormalized code 01011-01011-4) 1100-10000 10000 - unnormalized code. If the unit is in the lowest-order bit, then, by the property of normal codes, this unit is entered in the next-to-last low-order bit, and the extreme low is zeroed.

If there is a unit in the two higher bits, an overflow signal is generated. After. all possible convolutions are effected by the signal of block 1, trigger 7 goes to the zero state, and closes the pre. the former 4, and the device goes into storage mode,

In this mode, the binary code stored in drive 3 is monitored. If there are two units at the same time in the next bits of the code or if there is a unit in the last low-order bit, an error signal 1 appears at the output of control unit 5.

Thus, the proposed device allows you to expand the scope of application), which consists in storing and transmitting binary information.

normalization of binary Fibonacci codes and control of stored information. The device allows to significantly increase the reliability of the stored information in comparison with the known devices. If the probability of detecting an error of the type arising in the process of storing information presented in the classical binary number system in known i devices is O, then, Hanpjeje, when storing a 40-bit Fibonacci code in the proposed device, the error probability . attitude; the number of detected erroneous combinations to the volume of the number of possible 5. binary combinations is equal to 0.9999, i.e. 99.99% of the transitions from the allowed (normal) code combination to any possible are found.

Claims (2)

1. Kagan B.M. Electronic computers and systems. M., Energie, 1979, p. 87 2. Soloviev G. I. Arithmetic devices, computers. M., Energie, 1978 s. 77 (prototype.