SU875471A1 - Self-checking storage - Google Patents

Description

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This invention relates to memory devices.

A device is known that contains a drive connected to the input and output registers, the outputs of which are connected to the inputs of the control unit.

The disadvantage of this device is low speed.

Closest to the proposed technical solution is a self-monitoring Hutotaee device containing a drive, input and outgoing registers, a control unit, a delay element, and a control unit. In this device, the register outputs are connected to the control unit, the output of which is connected to the accumulator input connected with the control bit of the accumulator and to the counting inputs of the input register, the input of the delay element is connected to the output of the accumulator, and its output - to the counting inputs of the output register numbers

In this device, in the control recording of information in the accumulator cell, due to the lack of a functional connection between the output of the control unit and the input of the control unit, it is necessary to organize 3 cycles: writing, reading

and writing (inverted information and 1 in the check bit of non-inverted information and O in the check bit), and reading the written codes of numbers from the drive requires one read cycle: not 23.

However, due to the fact that in this storage device is missing

10 the separation of distorted and correct codes of readable numbers, it is possible to use. Devices only. two modes: control record mode and read mode. Besides,

15, this storage device, due to the additional control unit, is relatively complex and unreliable. . . . /. .

The purpose of the invention is to increase the speed and reliability of the device.

20

The goal is achieved by the fact that in a memory device with autonomous control, containing a drive, input and output registers,

25 is a delay element and a control unit, with one of the accumulator inputs connected to the output of the input register, and the outputs are connected respectively to one of the inputs in the register register and the input of the delay element whose output is;

thirty

connected to another input of the output register, one of the outputs of the control unit are connected respectively to the control inputs of the input and output registers and the accumulator, the BAN element and the AND element are entered, the first input of the AND element and the control input of the BAN element connected to the other output of the block control, the output of the output register is connected to the input of the control unit, the second input element I, one of the inputs of the input register and the other input of the accumulator, the information input of the element

APRET is connected with the output of the input register, and the output with another input

output register, output element AND is the output device.

The drawing shows a functional diagram of the device.

The storage device with autonomous control contains drive 1, INPUT 2 and output 3 registers, control block 4, delay element 5,. element 6 BAN, element AND 7.

Drive 1 is connected to input 2 and output 3 registers, information INPUT element b BANCH is connected to the output of input register 2, the control input is connected to the output of control unit 4 and the first input of AND 7, and the output is to the counting input of output register 3, output which, in turn, is connected to the accumulator input connected with the control bit of accumulator 1, to the count input of input register 2, to the input of control unit 4 and the second input of AND 7, the output of which is the output of the device.

U (the device works as follows.

The code of the number to be written enters the register 2. In the check-up mode, the code of the number is written to accumulator 1 and read into register 3. The information of the number code from the input register 2 is fed through the BAN element 6 also to the count input of the output register 3. At the same time The read information from accumulator 1 is written to the 3-digit register on the leading edge of the read signal, and the recording of information from the output of the input register 2 on the trailing edge of this signal. If the read and writeable information on the output and input of drive 1 is different,

then the output of the output register 3 will be a signal 1, indicating a negative result of the comparison, which is carried out by the output register 3.

This signal is fed to the counting input of register 2 by inverting the code of the number being written, to the input of accumulator 1 and to the input of the control unit 4.

The inverted number is written to the accumulator and 1 in its test bit at the same address, which is determined by the control unit 4.

When reading information from accumulator 1, the code of the number is written to register 3. In the case when the check digit of the requested address contains, the code of the number in register 3 is inverted by a signal from the output of the accumulator through the delay element 5 to the counting input of the output register 3. At the same time, correct information is restored.

Unit 4 controls the operation of the device with autonomous control in the wake {one mode:

a) a control recording mode, which consists of 2 cycles: writing and reading with a healthy cell of the accumulator and three cycles: writing, reading and writing (inverted information and 1 in the control bit) with a faulty cell of the accumulator;

b) the read mode of the recorded information storage device (one read cycle is required);

c) write - read mode, which combines the two previous modes of operation.

The input of the control unit is indicated by an error sign when comparing the codes of the recorded number in the control record mode.

The sign of completion of the control recording mode is generated by the control unit 4 after two cycles: writing and reading, when there is no comparison error, of the written and readable number at the output of the output register 3 or after three cycles: writing, reading and writing (inverted information and 1) de), in the presence of an error signal at the output of the output register 3.

An example. Let the code of the number to be written to the drive 1 have .View 01010, and the drive memory cells have faults of the type in neisBOM bit and 1 - “- O in the fourth bit. Then the information read from accumulator 1 and written to output register 3 in the record control mode will be 11000.

Claims (2)

Since the type of the recorded number (Q1010) is stored on the input register 2 and enters through the BANNER element 6 also to the counting input of the output register 3, the information on the output register 3 will look like 10010. At the output of the output register 3, there are errors in operation of the storage device. The signal 1 from the output of the output register 3 is fed to the counting input of the input register 2, inverting the code of the recorded number, to the input of the accumulator 1 and to the input of the control unit 4. The information in the input register is changed to 10101 and in this form is written into the drive 1. The inverted number is written to the drive and 1 in its check bit occurs at the same address. When reading information from accumulator 1, the number code is written to the output register 3. When reading information at the address where there were malfunctions of the memory cell in the first () and fourth () bits of the accumulator 1, 10101 is written on the output register and, as the check bit at the requested address contains 1, the code of the number in the output register is inverted by a signal coming from the drive through the delay element 5 to the count input of the output register 3. Recording information from the input register 2 to output 3 is blocked Subject B BAN. The reading of the number code is made through the AND 7 element, to one input of which a signal is sent indicating the completion of the check record mode, and to the other - the code of the number of read information from the output register. If there are no faults in the memory cells of the accumulator 1, the output of register 3 in the control record mode will be all zeros. Thus, for example, from the output of accumulator 1, the code of the number 01010 and the same information (01010) are written to the output register 3, and the same information (01010) is fed to the counting input of the output register 3 from the output of the input register 2 through the element b. It can be seen that at the output of the output register 3 there will be all zeros (O), as a result of which the code of the recorded number on the input register and writing 1 to the check digit on the drive 1 are not inverted. When reading information from the drive 1 to the output register 3 the code of the readable number is not inverted. The issuance of the code of the readable number occurs through the element And 7. Thus, the proposed device has the property to carry out self-control and correction of the information written to the drive. At the same time, having the same properties as the known device, it differs with additional properties and capabilities, namely: a) higher speed due to the fact that in the monitoring recording mode, the known device always needs 3 cycles: recording ,, reading and writing, and in the described storage device there can be 2 cycles: writing and reading when the drive cells are in good order or 3 cycles: writing, reading and writing in case of a drive cell fault. Thus, the described device has a speed of 1.5 times higher than the known; b) a larger area of application, since the device allows organizing one more mode of operation: writing - reading, which is important, for example, when building a computer, in greater reliability due to exclusion of a special information control unit from the device. The invention is a self-monitoring control device comprising a drive, input and output registers, a delay element and a control unit, one of the drive inputs connected to the output of the input register and the outputs connected to one of them. the inputs of the output register and the input of the delay element, the output of which is connected to another input of the output register, one of the outputs of the control unit are connected respectively to the control inputs of the input and output registers and accumulator, characterized in that, in order to improve the speed and reliability of the device, it contains the BANGE element and the AND element, the first input of the AND element and the control input of the BANGE element are connected to another output of the control unit, the output of the output register is connected to. the input of the control unit, the second input of the AND element, one of the inputs of the input register and the other input of the accumulator; the information input of the BAN element is connected to the output-input register, and the output is connected to another input of the output register; the output of the AND element is the output of the device. Sources of information taken into account in the examination 1. The author's certificate of SSRR № 367460, C. a 11 C 29/00, 1971. 2. USSR author's certificate number 497639, cl. 11 C 29/00, 1974 (prototype). 5f 6