RU1774502C - Redundancy code checking device - Google Patents

Abstract

The device for monitoring redundant codes relates to computer technology, and may find application in systems for storing, processing and transmitting discrete information. The device allows you to control L- and F-codes. based on extended into the region of negative argument values sequences of Luc and Fibonacci numbers. The device comprises a memory unit 3, a comparison circuit 4. 1 ill.

Description

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The invention relates to computer technology and may find application in information storage, processing and transmission systems.

A device for controlling Fibonacci p-codes is known, which contains a register, an OR element, n-p blocks for fixing faults and a group of p-p + 1 OR 1 elements. This device is based on the principle of monitoring redundant codes for compliance with a minimum form attribute.

The disadvantage of this device is the low efficiency of the control, which is explained by the impossibility of detecting errors of type O in 1 if the code has retained the minimum form flag, as well as all errors of type O that occurred before the controlled code was written to the register.

Closest to the present invention is a device for generating a positional sign in modular arithmetic, comprising a memory unit for storing constants, a summing unit, and a circuit for comparing the summing results with a constant, which is controlled by tabular conversion and analysis of its result 2.

The disadvantage of this device is the inability to control the F and L codes.

The purpose of the invention is to expand the scope.

The goal is achieved in that in a device containing a memory unit and a comparison circuit, wherein the clock input of the device is connected to the read enable input of the memory unit, the output of the comparison circuit is the output of the device, new communications are introduced, namely information inputs with (i + 1) -ro in the nth group of the device (n is the number of bits in the code; f is the number of bits in the code that has zero weight for the F code and a weight of two for the L code) are connected respectively to the address inputs of the group a memory unit whose group outputs are connected to the corresponding inputs the first group of the comparison circuit, information inputs from the first to the first group of the device are connected to the corresponding inputs of the second group of the comparison circuit

F and L codes are monitored according to the unambiguous correspondence of the left side () of the code images of their right side (I Ј 0).

For this purpose, in the proposed technical solution, on the left side of the source code being monitored, the corresponding right part is selected from the memory block, which is then compared with the right side of the source code. Their mismatch

indicates an error in the controlled code.

Moreover, if an error occurred on the right side of the code, then when comparing this part of the source code with the correct right side of the code read from the memory block, any errors will be detected. If there are any errors only on the left side of the memory block, the right part 0 of the code will be read, which does not correspond to the correct right side of the controlled code. In this case, only those errors that led to the code images of numbers having the same right-hand sides 5 will not be detected. For example, a type 1 error in O will not be detected in the first digit of the code of number 8, which can be seen when analyzing the table.

If there are errors in both parts of the code images, those 0 errors will not be detected that will lead to the allowed code combinations, i.e. to the code images of the F and L code of other natural numbers.

Thus, the proposed method

5 control allows control

discrete information in F- and L-codes with

greater efficiency than known

redundant code control devices,

exercising control on the basis of compliance with the minimum form.

The distinguishing features introduced are significant, since similar features were not found in the known solutions, and their combination of 5 makes it possible to achieve the goal.

The drawing shows a structural diagram of a control device.

The device contains a group of information inputs of the device, where 1 is information inputs 0 from (H-1) -th to the n-th group, 2 - information inputs from the first to the 1st group, memory block 3, comparison circuit 4, device output 5, clock input 6 of the device.

5 The inputs 1 of the group of information inputs of the device are connected respectively to the address inputs of the group of the memory block 3, the outputs of which are connected to the corresponding inputs of the first group of the comparison circuit 4 0, the inputs of the second group of which are connected to the information inputs of the device group 2, the output of the comparison circuit 4 is an output 5 of the device, the clock input 6 of the device is connected to the read enable input 55 of the memory unit 3. . Source controlled code should be presented in a minimal form.

In block 3 of the memory previously at the addresses equal to the left parts of all possible code combinations for a given

bits of the controlled code, the corresponding right parts are recorded. At the remaining addresses, words are written, in each row of which 1 is written, i.e. code combination that cannot be in F and L codes.

The device operates as follows.

When an enable signal is received at clock input 6 from the memory unit 3 at the address corresponding to the code on inputs 1, a code is read, which is compared with the code received on the comparison circuit 4 with the input 2 of the device. The result of the comparison goes to the output 5 of the device.

Thus, the proposed device allows, in contrast to the prototype, to control F- and L-codes according to the principle of correspondence of the left side of the controlled code (high order bits) of a single code combination of the right side of the code. .

Claims (1)

SUMMARY OF THE INVENTION An apparatus for monitoring redundant codes comprising a memory unit and a comparison circuit, wherein the clock input of the device is connected to a read enable input of the memory unit, the output of the comparison circuit is an output of the device, characterized in that, in order to expand the scope by providing control of L- and F-codes, information inputs from the (1 + 1) -th to the nth group of the device (p is the number of bits in the code, I is the number of bits in the code having zero weight for the F-code and weight equal to two for the L-code) are connected respectively with waist band input block of memory, the outputs of which groups are connected to respective inputs of the first group of the comparison circuit, data inputs of the first group 1 devices are connected to corresponding inputs of the second group of the comparison circuit.