SU1478340A1 - Fibonacci p-code check unit - Google Patents

Abstract

The invention relates to computing and can be used to control information provided in P-Fibonacci codes. The aim of the invention is to increase the reliability of the control. The device contains triggers 1 ₁ -1 ₇ registers 1, adders 2 ₁ -2 ₆ modulo two, blocks 3 ₁ -3 ₄ failures, element OR 4, information and installation inputs 5 and 6, control output 7 devices, inputs 8- 10 blocks fixing failures. The block for fixing failures contains two elements AND, the element OR, two elements NOT. 1 hp f-ly, 2 ill.

Description

The invention relates to computer technology and can be used to control the information presented in p-Fibonacci codes.

The aim of the invention is to increase the reliability of control.

In FIG. 1 shows a diagram of a device for p = 2; in FIG. 2 is a diagram of a block for fixing failures.

The device contains triggers 1.1-

1.7 register 1, adders 2.1-2.6 modulo two, fault fixing blocks 3.1-3.4, OR element 4, information and installation inputs 5 and 6 of the device, control output 7 of the device, the first - third inputs of 8-10 fault fixing blocks.

The block for fixing failures contains elements AND 11 and 12, element OR 13, elements NOT 14 and 15.

Number systems with irrational bases are redundant in the sense of the plurality of forms of representation of the same number, except zero. Among them, a minimal form is distinguished, which is characterized by the absence of two adjacent units, and a partially expanded form containing an even number of units. The values of the bits of a partially expanded form T (i) are determined through the corresponding bits of the minimum form by the following recurrence expression

I

T (x) = M (i + 1) + M (i + p + 1), (1) where M (i) is the ith discharge of the minimum form *, 1—0.1, ..., η, p 1,2,3, ·. ·

Moreover, each unit of the minimum form code in the partially expanded form code is represented as a sequence

1,0 ... 0,1 p - 1

The minimum code distance for partially expanded codes is two. In a partially reversed form, the least significant bit with zero weight is added, and the highest one is always zero. For example, with p = 1 and η = 7, the minimum code form 0100101 is converted according to expression (1) to a partially expanded form 11011110.

The control feature of a partially expanded form is an even number of units in the code and a limit on the number of units in groups, which allows one to detect all errors of odd multiplicity and a high percentage of errors of even multiplicity. Control is carried out by analyzing the outputs of the line of convolution schemes modulo two, the inputs of which receive the corresponding bits of a partially expanded form. With the correct code combination, the outputs of the line of convolution schemes are modulo two (presence

blow groups of adjacent units. An error signal appears if this condition is violated. So for p = 1, an error signal appears when there are two adjacent units at the outputs of the line of convolution schemes modulo two.

In this case, the block for fixing failures degenerates into a two-input element I. For p = 2, the series of units at the outputs of the convolution scheme line modulo two with the number of units other than the number two are erroneous.

When p = 2, the device operates as follows.

Let the initial code combination 1011010 be written in the triggers 1.1-1.7. At the outputs of the convolution schemes modulo two, the code 011011 is set. There is no error signal at the output of the OR logic 4 element. If the initial combination has the form 0011010 (an error in the low order), at the outputs of the convolution schemes modulo two 2.1-

2.6, the code 111011 is set. At the same time, the presence of an error is indicated by the unit potential at the outputs of the convolution scheme modulo two 2.1 and the block for fixing faults 3.1.

Suppose that an error occurs in the first and sixth digits of the original · code combination, then it takes the form 0011000. At the outputs of the convolution schemes modulo two 2.1–2.6, the code 000100 is set.

I

The zero values of the outputs of the convolution schemes modulo two 2.5 and 2.3 and the unit value of the output of the convolution schemes modulo two 2.4 set the unit potential at the output of the And 11 element in block 3.3 for fixing failures. This potential through the OR element 12 of block 3.3 sets the OR element 4 to a single value, which indicates the fixing of an error.

Similarly, all errors are detected that lead to a violation of the parity of units in the original code combination and equality to two of the number of units in groups of units in the code at the output of convolution schemes modulo two 2.1-2.6,

Claims (2)

Claim 1. A device for controlling the p-code and Fibonacci, containing a register of η triggers (η-bit capacity of the controlled code), the unit inputs of which are the corresponding information inputs of the device, the zero 20 inputs of the triggers are combined and are the installation input of the device, fault fixing blocks, the outputs of which are connected with the corresponding inputs of the OR element, the output of which is the output of the device malfunction, characterized in that, in order to increase the reliability of the control, it introduces (p-1) adders modulo two, the output Each register trigger, except the last, is connected to the first input of the corresponding adder modulo two, the output of the last register trigger is connected to the second input of the last adder modulo two and the first input of the OR element., i-ro output (i = 3 ,. .., n-1) the modulo two adder is connected to the second input (il) -ro of the adder modulo two and the jth (j = 1, ..., p + 1) input (i + j - 3) - of the first block of fault fixing, the output of the second adder modulo two is connected to the second input of the first and third input of the second block of fault fixing and the second input of the first adder Odulov two, the output of which is coupled to a third input of the first fixing unit failures and last input OR gate. 2. The device according to claim 1, characterized in that the fault fixing unit contains p elements AND, p elements NOT element OR, the first input of the first element AND is combined with the input of the first element NOT and is the first input of the block fixing failures, the second inputs of elements AND are combined and are the second input of the fault fixing block, the jth input at p 3 (j = 3, ..., p) of the first element AND is combined with the input (j-1) -ro of the element 'NOT and with the jth inputs i -χ (i = j, ..., p) of the AND elements is the jth input of the fault fixing block, the (p + 1) -th input of the first AND element is combined with the input of the r-th element NOT and is the (p + 1) th input of the fault fixing block, the output of the first element is NOT connected to the first inputs of the elements AND, except for the first, the output i-ro (i = 2, ..., p) of the element is NOT connected to (i + D -th input of the i-ro element AND, the outputs of the elements AND are connected to the corresponding inputs of the OR element, the output of which is the output of the fault fixing block. 14 78340 Figure 2