SU1531175A1 - Memory - Google Patents

Abstract

The invention relates to memory devices and can be used in digital computers made on functional nodes with a high degree of integration. The purpose of the invention is to increase the speed of the storage device. This goal is achieved by introducing an error correctability block that contains the error multiplier 13, register group 15, switch 16, reference element 19, first group of elements OR 17, second group of elements OR 20, delay element 21, register 18, node 13 ti control groups. The memory device makes it possible to almost immediately determine the correctability of errors in a read word, as well as reduce, on average, by 50% the time for obtaining reliable information when accessing the drive cell with errors caused by failures of the storage elements. 1 hp ff, 2 ill.

Description

From7

FIG. 2

The invention relates to memory devices and can find a note (- in digital computers made on functional units with a high degree of integration.

The purpose of the invention is to increase the speed of the memory device.

FIG. 1 presents a structural diagram of a memory device, in FIG. 2 - block diagram of the error correctability check.

The storage device contains a memory block consisting of accumulator 1, address 2 and bit 3 blocks, register 4 addresses, forward 5 registers and inverse code 6, comparison block 7 counter 8, distributor 9 bad bits, encoding block 10, buffer register 11, block 12 of checking and correcting errors (local control unit that synchronizes the operation of all blocks of the storage device, not shown).

Unit 12 contains the UAE 13 memory of control groups, an error multiplication decoder 14, a register group 15, a switch 16, a first group 17 of OR elements, a register 18, a comparison element 19, a second group of OR elements 20, a delay element 21.

The device works as follows.

During the recording, the address of the cell to which information is to be written, which is supplied to block 10, is fed to the input of register 4.

In block 10, the word is encoded by the applied correction code and written to drive 1 via register 5 at a given address.

When reading, the address of the cell to which the information should be read goes to register 4, from where it is transmitted to block 2. The word at this address is read from accumulator 1 and through block 3 enters register 5 and block 10, where it is checked by means of control checks is there a mistake in the word. If there is no error, then the word goes to the system output.

In the event that an error has occurred, the word is inverted and written to drive 1 at the same address and read again, now register B is entered 6. Next, the word is transmitted from the inverse output of register 6 to block 10, where it is checked again for an error . If there is no error, then. c-pono goes to the output of the device. If so, then the contents of registers 5 and 6 go to block 7 comparison. At the output of this circuit, there are units in those in which the total of registers 5 and 6, i.e. in those categories in which failures occur. These units arrive at counter 8, and their location is transmitted to the distributor

9. Each state of the counter 8 through the distributor 9 enters the counting inputs of the register 5, after which the converted word is transmitted to the block

10, where each time it is checked for an error. Such checks are carried out until coding block 10 issues a signal that there is no error.

Simultaneously with the operation of the counter 8 for iterating through the combinations, the information about the failed bits comes from block 7 to the error correctness checking block 12, which determines whether the combination found by the search circuit in the positions of the failed bits will have a single decoding algorithm (i.e. true, reliable information after decoding) or not. This can be implemented, for example, in this way. A positional series of read bits enters the node 13 of the memory of the control groups, with the help of which it is determined by which control groups the failed bits are checked. This information is recorded by a group of registers .15, in which so many registers will be used, what is the multiplicity of the error specified in the decoder 14, namely, the first of the registers of group 15 are written to those control groups that check the first of the failed bits in the layers, in the second register — those control groups that check the second failed word and so on. In this case, 1 is recorded in the bit of each of the registers of group 13 if the corresponding control group checks this failed bit. Otherwise, O is written to the corresponding bit. At the end of the recording, the contents of the first two registers of group 15 through the group of bit elements OR 17 enters the register 18. Each subsequent word (third, fourth, etc.

515

from the registers of group 15, through switch 16, is read into comparing element 19. In this case, the switch 16 alternately feeds the input 19 of the element 19 (j-2 registers of group 15, where j is the failure rate, defined by group decoder 14 (i.e., the number of registers of group 15 involved in this case). 19, the logical disjunction of the first and second word of the same name (i.e., the contents of working register 18) is read and compared with the contents of the subsequent (initially third) register of group 15. If the next word is not equal to the contents of working register 18, then it finds c from the registers of group 15 through switch 16, a group of elements OR 20, a delay element 21 and is written to the working register 18, after which it is compared with the contents of the fourth register, etc., etc. This sequence of actions is repeated until either the last register of group 15 will be counted, or until the signal is received. The error is irreparable.

In the first case, the error will be correctable by iteration, i.e. The first word that will be formed by the counter 8 and which does not give out a signal. The decoding error is unrecoverable, it will be the only one that is being searched.

In the event that the comparison element 19 generates a signal Unrecoverable error, this means that the error cannot be unambiguously corrected by this sorting scheme.

Thus, the proposed storage device makes it possible to almost immediately determine the correctability of errors in a read word, reducing, on average, by 50% the time to obtain reliable information when accessing the drive cell with errors caused by failures of the storage elements.

Claims (2)

1. A storage device containing a memory block, direct and inverse code registers, a comparison block, a counter, a fault distributor, a coding block, a buffer register, information input and output of which are connected respectively to the first information output and input 56 the house of the coding unit, the second information input and output of which are respectively information input and output of the device, and the third information input and output are connected respectively to the first information output and input of the direct code register, the second information input and output of which are connected respectively to information output and the input of the memory block whose address inputs are the address inputs of the device, the input of the register of the inverted code is connected to the information output of the memory block, and the output connected to the fourth information input of the coding unit and the first input of the comparison unit, the second input of which is connected to the third information output of the direct code register, the first output of the comparison unit is connected to the input of the counter, the output of which is connected to the input of the number of faulty bits of the distributor of faulty bits, the input the position of the faulty bit of which is connected to the second step of the comparison unit, and the output of the distributor of the faulty bits is connected to the third information input of the direct code register, characterized in that, in order to improve the speed of the device, it contains an error correctability checker, the output of which is connected to the control input of the buffer register, and the input is connected to the third output of the comparison unit. 2. The device according to claim 1, of which is, that the error correctability checking unit contains an error multiplier decoder, a group of registers, a switch, an element of c5 Neni, two groups of elements OR, delay element, register, control group memory node whose input connected to the input of the error multiplier decoder and is the input of the error correction block n, the output of the control group memory node is connected to the first switch control input of the switch and to the first information input of the register group, the second information input of which is connected to the first information output of the error multiplicator, The second information loop of which is connected to the second switch control input of the switch, the output of which is connected to the first input of the comparison element, the second input of which th register coupled to the output, which is connected to the outputs onny Informational input OR elements of the first group, whose inputs are connected to respective outputs of the second and third group of registers, the output comparison element, Q FIG. /. It is the output of the error checker and is connected to the inverse inputs of the OR elements of the second group, the direct inputs of which are connected to the register output, the mode control input of which is connected to the output of the delay element, the input of which is connected to the outputs of the OR elements of the second group.