RU2297035C2 - Fault-tolerant memorizing device - Google Patents

Abstract

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

Description

The invention relates to computer technology and can be used to increase the reliability of the operation of combinational devices, as well as devices for storing and transmitting information (operational and read-only memory computers, etc.).

A self-correcting discrete device [1] is known that uses a decoding device that corrects modular (byte) errors based on the use of Reed-Solomon codes containing the original circuit, the encoding device, the redundant circuit, the decoding device, including the syndrome calculation circuit, the imaginary syndrome shaper, the error decoder in byte, distorted byte calculation circuit, error switches, error corrector, device inputs are connected to the inputs of the original circuit and to the inputs of the encoder, code outputs the switching device is connected to the inputs of the redundant circuit, the outputs of which are connected to the first inputs of the syndrome calculation circuit, the outputs of the original circuit are connected to the second inputs of the syndrome calculation circuit and to the first inputs of the corrector, the outputs of the syndrome calculation circuit are connected to the inputs of the error decoder, the outputs of which are connected to the second inputs corrector, corrector outputs are device outputs.

The disadvantage of this device is the low reliability of the device, since the Reed-Solomon codes allow you to correct the error in one byte of information and detect an error in two bytes of information.

The closest in technical solution is a self-correcting discrete device [2], containing the original circuit, the first coding device, the error syndrome scheme, error decoder, corrector, the second, third and fourth encoding devices, the first to fourth convolution schemes, error symptom scheme, element OR, the inputs of the device are connected to the original circuit and to the inputs of the first encoding device, to the inputs of the second encoding device, and the outputs of the original circuit are connected to the inputs of the third and fourth encoding devices properties to the first inputs of the corrector, the outputs of which are the outputs of the device, the outputs from the first to fourth encoding devices are connected respectively to the inputs from the first to fourth convolution schemes, the outputs of the first and third convolution schemes are connected to the inputs of the error syndrome circuit, the outputs of the second and fourth convolution schemes connected to the inputs of the error flag circuit, the outputs of the error syndrome circuit and the error flag are connected to the inputs of the error decoder, the first group of outputs of the error decoder is connected to the second inputs of the corrector, and the second The output group is connected to the input of the OR element, the output of which is the signal “device failure”.

The disadvantage of this device is the low reliability of operation, since errors that occur simultaneously in information and control discharges are not corrected.

The aim of the invention is to increase the reliability of the operation of the device by correcting 88% of detected errors that do not exceed the multiplicity of k-1, subject to the maximum detection of the number of errors in the code set.

This goal is achieved in that the device containing the original circuit, the encoding device, the scheme of the error syndrome, the decoder, the corrector, the information inputs of the device are connected to the first inputs of the original circuit, the outputs of which are connected to the first inputs of the corrector, the outputs of the corrector are the outputs of the device, characterized in that it additionally contains first to fifth AND elements, first to eighth OR elements, a parity check circuit, an inversion block, a register, a NOT element, address inputs, write input, read input input, "Reset" input, and the information inputs of the device are connected to the first inputs of the first element And, the address inputs are connected to the second inputs of the original circuit and to the first inputs of the register, the recording input is connected to the third input of the original circuit, to the second input of the first element And and to the second input of the register, the read input is connected to the fourth input of the original circuit, to the first input of the second element And, to the first input of the third element And, to the first input of the fourth element And to the third input of the register, the input "Reset" is connected to the fifth input and the input circuit and the fourth input of the register, the outputs of the original circuit are connected to the second inputs of the second AND element, the outputs of which are connected to the first inputs of the first OR element, the second inputs of which are connected to the outputs of the first AND element, and the outputs are connected to the inputs of the parity circuit, to the inputs of the inversion unit and to the first inputs of the encoder, the output of the parity check circuit is connected to the second input of the encoder, the outputs of the inversion unit are connected to the third inputs of the encoder, the outputs of the encoder the devices are connected to the second inputs of the third AND element and to the fifth inputs of the register, the first inputs of the error syndrome circuit are connected to the outputs of the third AND element, the second inputs are connected to the outputs of the register, and the outputs are connected to the inputs of the decoder and to the inputs of the second OR element, the output of which is connected to the first input of the fifth AND element, the first group of decoder outputs is connected to the inputs of the third OR element, the second group of decoder outputs is connected to the inputs of the fourth OR element, the third group of decoder outputs is connected to the inputs of the fifth OR element, the fourth group of decoder outputs is connected to the inputs of the sixth OR element, the fifth group of decoder outputs is connected to the inputs of the seventh OR element, the outputs from the third to sixth OR elements are connected respectively from the second to fifth inputs of the fourth AND element and from the first to fourth the inputs of the eighth OR element, the output of the seventh OR element is connected to the fifth input of the eighth OR element, the output of which through the element is NOT connected to the second input of the fifth AND element, the input of the fifth AND element is the output home device, the outputs of the fourth AND gate connected to the second inputs of the corrector.

The drawing shows a block diagram of a device.

The device contains the original circuit 1, the first element 2 AND, the second element 3 AND, the third element 4 AND, the fourth element 5 AND, the fifth element 6 AND, the first element 7 OR, the second element 8 OR, the third element 9 OR, the fourth element 10 OR , fifth element 11 OR, sixth element 12 OR, seventh element 13 OR, eighth element 14, coding device 15, error syndrome circuit 16, decoder 17, corrector 18, parity check circuit 19, inversion unit 20, register 21, element 22 NOT, information inputs 23, address inputs 24, input 25 records, input 26 reads, input 27 reset, outputs 2 8 devices, output 29 "Device failure".

Information inputs 23 of the device are connected to the first inputs of the first element 2 And to the first inputs of the original circuit 1, the outputs of which are connected to the first inputs of the corrector 18, the address inputs 24 are connected to the second inputs of the original circuit 1 and to the first inputs of the register 21, the input 25 of the record is connected to the third input of the original circuit 1, to the second input of the first element 2 AND and to the second input of the register 21, the input 26 of the reading is connected to the fourth input of the original circuit 1, to the first input of the second element 3 And, to the first input of the third element 4 And, to the first input a quarter of the fifth element 5 And and to the third input of the register 21, the input 27 "Reset" is connected to the fifth input of the original circuit 1 and the fourth input of the register 21, the outputs of the original circuit 1 are connected to the second inputs of the second element 3 And, the outputs of which are connected to the first inputs of the first element 7 OR, the second inputs of which are connected to the outputs of the first element 2 AND, and the outputs are connected to the inputs of the parity checking circuit 19, to the inputs of the inversion unit 20 and to the first inputs of the encoding device 15, the output of the parity checking circuit 19 is connected to the second input of the coding device VA 15, the outputs of the inversion unit 20 are connected to the third inputs of the encoder 15, the outputs of the encoder 15 are connected to the second inputs of the third element 4 AND and to the fifth inputs of the register 21, the first inputs of the circuit 16 of the error syndromes are connected to the outputs of the third element 4 AND, the second inputs connected to the outputs of the register 21, and the outputs are connected to the inputs of the decoder 17 and to the inputs of the second element 8 OR, the output of which is connected to the first input of the fifth element 6 AND, the first group of outputs of the decoder 17 is connected to the inputs of the third element 9 OR, the second the group of outputs of the decoder 17 is connected to the inputs of the fourth element 10 OR, the third group of outputs of the decoder 17 is connected to the inputs of the fifth element 11 OR, the fourth group of outputs of the decoder 17 is connected to the inputs of the sixth element 12 OR, the fifth group of outputs of the decoder 17 is connected to the inputs of the seventh element 13 OR , the outputs from the third 9 to the sixth 12 elements OR are connected respectively from the second to fifth inputs of the fourth element 5 AND and from the first to fourth inputs of the eighth element 14 OR, the output of the seventh element 13 OR is connected to the fifth input dy eighth OR element 14, through which output member 21 is not connected to the second input of the fifth AND element 6, the fifth input element 6 and is the output device outputs the fourth element 5 and connected to the second inputs of the equalizer 18.

The parity check circuit 19 is intended to generate a parity check digit value relative to information bits.

Block 20 inversion is designed to invert the values of the information bits coming from the outputs of the first element 7 OR, respectively, when writing and reading information.

In the encoding device 15 information bits and a parity bit are presented in the form of a two-line information matrix:

r_ЧЕТ,

- соответственно прямые и обратные значения i-го информационного разряда и значения разряда четности кодового набора.where _i

r _EVEN

- respectively, direct and inverse values of the i-th information bit and the values of the parity bit of the code set.

Regarding the formed matrix in the encoder 15, right and left diagonal checks are performed.

The number of diagonal checks (the number of control bits) is determined by the formula:

R _D = 2 (k + 2).

When reading information, the encoding device 15 generates (in the same way) a vector of control bits R ^{P of the} received code set.

Thus, during the period of writing and reading information, at the output of the encoder 15 we have, respectively, the vectors of the control bits:

R = r ₁ r ₂ ......................................., r _{2 (k +2)} ,

R ^P = r ₁ ^P r ^P .................................... r ^P _{2 (k + 2)} .

Scheme 16 of the error syndrome is intended for bitwise comparison of the values of the control bits obtained by transmitting the code set and generated relative to the received values of the information bits, and represent a set of adders mod 2 (according to the number of control bits).

The result of adding, according to mod 2, the signal values of the transmitted and generated control bits will give an error syndrome:

E = e ₁ e ₂ e ₃ ........... e _{2 (k + 2)} .

The decoder 17 contains 2 (k + 2) inputs (the number of bits of the error syndrome) and L = l ₁ + l ₂ + l ₃ outputs (according to the number of matching circuits, which are 2 (k + 2) input circuits I), where

- l ₁ - group of elements And (for various syndromes that characterize errors only in information bits;

- l ₂ - group of elements And (for various syndromes that characterize errors only in the control bits;

- l ₃ - group of elements And (for syndromes characterizing errors that occur simultaneously in information and control discharges.

In the event of errors at one of its outputs, a single signal is generated.

The outputs of the decoder 17 are combined, respectively, into one output using the third element 9 OR, the fourth element 10 OR, the fifth element 11 OR, the sixth (k-th) element 12 OR to generate control signals for the corrector, respectively, to correct the first, second ... k-th information bits.

The seventh OR element 13 combines the outputs of the decoder 17 (the outputs of the circuits AND), belonging to the subset l ₂ and corresponding to the occurrence of errors only in the control bits (for which the formation of control signals to the corrector is not required).

, возникающих на выходах исходной схемы 1.The corrector 18 includes k elements of ambiguity and is designed to correct errors

arising at the outputs of the original circuit 1.

When correcting errors, a function is implemented relative to the control signals u _i coming from the outputs of the OR elements:

The register 21 is designed to store the values of the signals of the vector of the control bits formed when recording information in the original circuit 1.

If errors occur that belong to a subset of n ₁ - for the same syndromes, indicating an error in different information bits (having the same meaning of the syndromes and additional checks, see the appendix), characterized by the presence of single values at the output of the circuit 16 error syndromes, and the absence of single values on the outputs from the third 9 to the seventh 13 elements OR, using the second element 8 OR, the eighth element 14 OR, element 22 NOT, the fifth element 6 AND the signal is generated ″ Device failure ″.

The device operates as follows. Before starting work, a signal is applied to input 27, which sets the device to its initial state. Upon receipt of input information at information inputs 23, address inputs 24 and the signal “Record” to input 25, information is recorded at the specified address in the original circuit 1. At the same time, it is fed to the inputs of the first element 2 AND, opened by the signal from input 25, and then through the element 7 OR the input information is supplied to the first inputs of the encoding device 15, to the input of the parity check circuit 19 and to the inputs of the inversion unit 20. The second input of the encoding device 15 receives the values of the parity of the information bits, and to The inverse values of the information bits are received from the inputs, and a two-line information matrix is formed from the obtained parity bit, direct and inverse values of the information bits, with respect to which the right and left diagonal checks are organized in the encoding device 15 implemented on the adder group mod 2.

From the outputs of the encoder 15, the value of the vector of control bits is fed to the input of the register 21 and is recorded at the specified address.

When reading information at the specified address, the signals from the output of the original circuit 1 through the second AND element 3, opened by the "Read" signal from input 26, the OR element 7 is repeatedly fed to the input of the encoding device 15, where the signal values are generated in the control bits relative to the information matrix formed according to the information received.

In this case, the information from the outputs of the encoding device 15 through the third element 4 And goes to the first inputs of the circuit 16 of the error syndrome, the second inputs of which receive information read from the register 21.

Scheme 16 of the error syndrome performs bitwise comparison of the values of the received control bits and formed relative to the received information.

As a result, at the output of the error syndrome circuit 16, we have the generated value of the error syndrome.

The decoder 17 when an error occurs generates a single signal at one of its outputs in accordance with the incoming value of the error syndrome. Depending on the number of the information category having an error, a control signal will appear at the output of the corresponding (9 ... 12) OR element. This signal through the open fourth element 5 And is fed to the input of the corrector 18, where there is a correction of erroneous information discharge.

If the error occurred only in the control bits, the signal appears at the output of the seventh element 13 OR (no control signals to the corrector are required).

The outputs of the decoder 17 are combined, respectively, into one output using the third element 9 OR, the fourth element 10 OR, the fifth element 11 OR, the sixth (k-th) element 12 OR to generate control signals for the corrector, respectively, to correct the first, second ... k-th information bits.

The seventh OR element 13 combines the outputs of the decoder 17 (the outputs of the circuits AND), belonging to the subset l ₂ and corresponding to the occurrence of errors only in the control bits (for which the formation of control signals to the corrector is not required).

, возникающих на выходах исходной схемы 1. При исправлении ошибок реализуется функция относительно управляющих сигналов u_i, поступающих с выходов элементов ИЛИ:The corrector 18 includes k elements of ambiguity and is designed to correct errors

arising at the outputs of the original circuit 1. When correcting errors, a function is implemented with respect to the control signals u _i coming from the outputs of the OR elements:

If errors occur that belong to the subset n ₁ - for the same syndromes, indicating an error in different information bits (having the same value of the syndromes and additional checks, see the appendix), characterized by the presence of unit values at the output of the circuit 16 error syndromes and the absence of unit values at the outputs from the third 9 to the seventh 13 elements OR, using the second element 8 OR, the eighth element 14 OR, element 21 NOT, the fifth element 6 AND the signal "Device failure" is generated.

application

Error correction of a given multiplicity, provided that errors are detected in the remaining bits of information, can be achieved based on an iterative code.

The procedure for constructing a two-dimensional iterative code is as follows [3]. A given set of information symbols is divided into groups (blocks, modules) of information, by b-bits in each group. The resulting information modules are presented in the form of an information matrix (1):

Then the information is encoded using the parity method (by adding mod 2 characters of rows and columns of the resulting matrix). As a result, we have a two-dimensional iterative code that allows us to detect and correct any single error:

where H = h ₁ , h ₂ , ..., h _m is the line parity vector; Z = z ₁ , z ₂ , ..., z _b is the column parity vector. The parity vectors of rows and columns form the set of control bits R ₁ = {r ₁ , r ₂ , r _m , r _{m + 1} , ..., r _b }. Upon receipt of the code combination relative to the information bits, the values of the control bits R ₁ ^P = {r ₁ , r ₂ , r _m , r _{m + 1} , ..., r _b } are re-formed. In this case, the difference between the transmitted values of the control bits and received after receiving the information forms the error syndrome E:

In this case, the bits of the error syndrome e ₁ e ₂ ... e _m (obtained with respect to the row parity vector) indicate the module of information with an error, and the bits e _m e _{m + 1} ... e _b (obtained with respect to the column parity vector) indicate bit in the information module.

Since code combinations of rows and columns have a minimum distance d = 2, the minimum distance of this code is d = 4. This code allows you to correct any single error and detect a significant proportion of multiple errors.

The structures of errors not detected by the two-dimensional iterative code are shown in the figure:

Fig. 1. Structures of errors not detected by a two-dimensional iterative code: a) errors of multiplicity 4; b) - errors of multiplicity 6.

Fig. 2. Error structures of a two-dimensional iterative code leading to erroneous correction: a) errors of multiplicity 5; b) - errors of multiplicity 7.

In the general case, iterative codes of higher dimension can be constructed (three-dimensional, four-dimensional, etc.), where each information symbol will be a component of x different codewords at the same time. The parameters of iterative codes of dimension x are as follows [3]:

where n _i , k _i , d _i are the length, the number of information bits, the minimum distance of the code sets of rows and columns, respectively.

Based on this, to build iterative codes should use checks that have the highest detecting ability.

Thus, the organization of diagonal checks of the matrix under consideration will allow us to identify error structures that are not detected by an iterative code that implements parity checks of rows and columns.

The structure of diagonal checks that detect the considered errors has the form shown in Fig. 3.

Left diagonal checks are formed according to the rule:

The results of the right diagonal checks are formed by summing the values of the following information bits:

In this case, the total number of diagonal checks is 2l, or:

Example 1. Let the word in question consists of four information bits that have zero meanings. For this code set, the information matrix has the form:

In this case, checks for the parity of rows and columns of the information matrix will give zero values and, in addition, the results of all right and left diagonal checks will have zero values. If an error occurs in all information bits, we have an even error that cannot be detected by a two-dimensional iterative code, because parity checks of rows and columns of the information matrix have zero values:

At the same time, the right and left diagonal checks will give a result of 101.

Proposition 1. An iterative code that implements right and left diagonal checks detects all even errors that are not detected by the two-dimensional iterative code, and identifies odd errors that are perceived by the two-dimensional iterative code as correctable.

In turn, there are error structures that are not detected by iterative code that implements right and left diagonal checks and checks for the parity of rows and columns. The structures of the considered errors are presented in Fig. 4.

Fig. 4. Error structures not detected by diagonal checks and row and column checks.

So, for example, with respect to the information matrix having zero values, the following error structure will not be detected by diagonal checks.

In order to exclude the appearance of the considered errors, the information matrix should contain no more than two rows.

Proposition 2. For an information matrix b × 2, an iterative code that implements right and left diagonal checks detects the maximum number of possible errors (except for the set of 2 ^k -1 forbidden code sets that can be transformed into allowed code sets).

Thus, when using an iterative code that implements right and left diagonal checks and parity checks, the code set is transmitted in the form:

For this example, the encoding of information is as follows:

r ₁ = y ₁ ; r ₂ = y ₂ ⊕y ₃ ; r ₃ = y ₄ ; r ₄ = y ₃ ; r ₅ = y ₁ ⊕y ₄ ; r ₆ = y ₂ .

The result of adding the values of the signals of the control bits transmitted and received will give an error syndrome:

where the bits of the error vector r ₁ , r ₂ ............... r _l - correspond to the right diagonal check, r _l , r _{l + 1} ........... .... r _2l - left and formed relative to the received information bits;

- значения полученных контрольных разрядов.

- the values of the received control bits.

Property 1. There are such error configurations in information and control bits for which the error syndromes have the same meanings.

To distinguish these errors, when generating the values of the error syndromes, additional diagonal checks are organized:

Thus, each error from the set of errors M = (2 ⁿ ) k can be associated with the value of the error syndrome and the value of additional diagonal checks.

Property 2. Each set of values of the error syndrome and the value of additional checks corresponds to a subset of Q-errors of various configurations.

Corollary 1. To distinguish between errors belonging to this subset, it is necessary to limit the multiplicity of correctable errors and increase the number of control bits (perform additional coding of information bits).

In this regard, the proposed encoding method includes the following provisions:

1) in order to ensure the correction of 88% of errors that occur, it is advisable to limit itself to correcting errors whose multiplicity does not exceed k-1;

2) checks for the parity of information bits;

3) from the direct inverse values of the information bits and the obtained value of the parity bit, an information matrix is formed:

4) for the obtained information matrix, right and left diagonal checks are organized. The number of diagonal checks (the number of control bits) is determined by the formula:

5) the code set is transmitted in the form:

6) the result of adding the signal values of the transmitted and generated control bits will give an error syndrome:

7) when the error syndrome is formed with respect to the received and generated values of the control bits, additional diagonal checks are organized, the number of which is determined by the expression:

), характеризующихся определенными значением синдрома ошибки и дополнительной проверки.8) as a result, we have many errors of a given multiplicity (in this case, from single to multiplicity k-1, defined by the expression:

) characterized by a certain value of the error syndrome and additional verification.

9) the set N is divided into four subsets N = n ₁ + n ₂ + n ₃ + n ₄ , where

n ₁ - syndromes having the same additional checks (uncorrectable errors, a sign of device failure);

n ₂ is a subset of groups (each group includes 2 ^k- identical values of the syndromes) in the presence of errors only in information bits;

n ₃ - a subset of groups (each group includes 2 ^k- identical values of the syndromes) in the presence of errors only in the control bits;

n ₄ is a subset of groups (each group includes 2 ^k- identical values of the syndromes) in the presence of errors simultaneously in the information and control bits.

Note that for errors not exceeding the multiplicity k-1, there are no erroneous code sets that can be transformed into allowed (serviceable) code sets.

Based on the obtained coding rules, a decoding strategy is formed that solves the problem of distinguishing errors in information and control bits and the rules for correcting errors that arise, which includes the following points:

1) identical additional checks are revealed, according to which error syndromes belonging to the subset n ₁ are excluded from the set N (uncorrectable errors are detected for which the "Device failure" signal is generated);

2) groups of identical syndromes (indicating an error in the corresponding information bits) are determined for the subset n ₂ ;

3) groups of error syndromes belonging to a subset of n _{3 are} determined for which correction of information bits is not required;

4) groups of the same values of the error syndromes belonging to the subset n ₄ and that allow correcting errors in the corresponding information bits are revealed.

For the considered example that implements the proposed encoding method, we have:

- the total number of errors is 11136;

- the number of identical error syndromes having the same additional checks (subset n ₁ ) - 1272 (the number of detected errors);

- 9864 - the number of correctable errors (88%);

- the number of errors only in information categories is 224 (l ₁ = 14-groups, each of which includes 16 identical syndromes);

- the number of errors only in the control bits is 4416 (l ₂ = 276 groups, each of which includes 16 identical syndromes);

- the number of errors having distortions simultaneously in the information and control bits is 5224 (l ₃ = 326 groups, each of which includes 16 identical syndromes, 1 group includes 7 identical syndromes, 1 group represents one value of the syndrome).

Table 1 shows a part of the values of the error syndromes for the subsets n ₂ , n ₃ , n ₄ . (excluded are the syndromes of errors of the subset n ₁ having the same values of additional checks).

The proposed encoding method allows you to:

Correct an error of a given multiplicity;

detect the maximum number of errors (with the exception of erroneous code sets that are transformed into allowed code sets);

signal a malfunction of the memory device when an uncorrectable error occurs.

Information sources

1. Scherbakov N.S. The reliability of digital devices. M.: Engineering, 1989, 224 p., Fig. 39, Fig. 44.

2. A positive decision on the application (21) 99111190/09 dated 01/15/03 (filed May 31, 09), authors: Tsarkov AN, Bezrodny B.Yu., Novikov NN, Romanenko Yu.A., Pavlov A.A.

3. Khetagurov Y. A. Rudnev Yu.P. Improving the reliability of digital devices using redundant coding methods. M .: Energy, 1974, 270 p.

Claims (1)

A fault-tolerant storage device containing a storage device, an encoding device designed for performing right and left diagonal checks and forming a vector of control bits, an error syndrome diagram, a decoder, a corrector designed to correct errors that occur at the outputs of the storage device, the information inputs of the device are connected to the first the inputs of the storage device, the outputs of which are connected to the first inputs of the corrector, the outputs of the corrector are the outputs of the device property, characterized in that it additionally contains from the first to the fourth group of AND elements, the fifth AND element, the first group of OR elements, the second to eighth OR elements, the parity check circuit, inversion block, register, NOT element, address inputs, input write, read input, input "Reset", and the information inputs of the device are connected to the first inputs of the elements And of the first group, the address inputs are connected to the second inputs of the storage device and to the first inputs of the register, the write input is connected to the third input of the storage device devices, to the combined second inputs of the AND elements of the first group and to the second input of the register, the read input is connected to the fourth input of the storage device, to the combined first inputs of the elements AND of the second group, to the combined first inputs of the elements AND of the third group, to the combined first inputs of the elements AND of the fourth group and to the third input of the register, the input "Reset" is connected to the fifth input of the storage device and to the fourth input of the register, the outputs of the storage device are connected to the second inputs of the elements of the second group, the outputs of which are connected to the first inputs of the elements OR groups of elements OR, the second inputs of which are connected to the outputs of the elements AND of the first group, and the outputs are connected to the inputs of the parity check circuit, to the inputs of the inversion unit and to the first inputs of the encoder, the output of the parity check circuit is connected to the second input of the encoder, the outputs of the inversion unit are connected to the third inputs of the encoder, the outputs of the encoder are connected to the second inputs of the AND elements of the third group and to the fifth inputs of the register, the first inputs of the error syndrome circuit are connected to the outputs of the AND elements of the third group, the second inputs are connected to the outputs of the register, and the outputs are connected to the inputs of the decoder and to the inputs of the second OR element, the output of which is connected to the first input of the fifth AND element, the first group of outputs of the decoder is connected to the inputs of the third OR element, the second group of decoder outputs connected to the inputs of the fourth OR element, the third group of decoder outputs connected to the inputs of the fifth OR element, the fourth group of decoder outputs connected to the inputs of the sixth OR element, the fifth group of decoder outputs is connected to the inputs of the seventh OR element, the outputs from the third to sixth elements OR are connected to the second inputs of the AND elements of the fourth group and from the first to fourth inputs of the eighth OR element, the output of the seventh OR element is connected to the fifth input of the eighth OR element, the output of which through the element is NOT connected to the second input of the fifth AND element, the output of the fifth AND element is the “Device Failure” output, the outputs of the AND elements of the fourth group are connected to the second inputs correctly ora.