RU2297034C2 - Fault-tolerant information storage device - Google Patents

Abstract

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, inversion block, decoder, even parity check circuit, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

Description

The invention relates to computer technology and can be used to increase the reliability of the operation of combinational devices, as well as storage and transmission devices (online and read-only memory computers, etc.).

It is known self-correcting discrete device [1], using a decoding device that corrects modular (byte) errors based on the use of Reed-Solomon codes, containing the original circuit, encoding device, redundant circuit, decoding device, including a syndrome calculation circuit, an imaginary syndrome shaper, an error decoder in byte, distorted byte calculation circuit, error switches, error corrector, device inputs are connected to the inputs of the original circuit and to the inputs of the encoder, code outputs the switching device is connected to the inputs of the redundant circuit, the outputs of which are connected to the first inputs of the syndrome calculation circuit, the outputs of the original circuit are connected to the second inputs of the syndrome calculation circuit and the first inputs of the corrector, the outputs of the syndrome calculation circuit are connected to the inputs of the error decoder, the outputs of which are connected to the second inputs corrector, corrector outputs are device outputs.

The disadvantage of this device is the low reliability of the device, since the Reed-Solomon codes allow you to correct the error in one byte of information and detect an error in two bytes of information.

The closest in technical solution is a self-correcting discrete device [2], containing the original circuit, the first coding device, the error syndrome scheme, error decoder, corrector, the second, third and fourth encoding devices, the first to fourth convolution schemes, error symptom scheme, element OR, the inputs of the device are connected to the original circuit and to the inputs of the first encoding device, to the inputs of the second encoding device, and the outputs of the original circuit are connected to the inputs of the third and fourth encoding devices properties to the first inputs of the corrector, the outputs of which are the outputs of the device, the outputs from the first to fourth encoding devices are connected respectively to the inputs from the first to fourth convolution schemes, the outputs of the first and third convolution schemes are connected to the inputs of the error syndrome circuit, the outputs of the second and fourth convolution schemes connected to the inputs of the error flag circuit, the outputs of the error syndrome circuit and the error flag are connected to the inputs of the error decoder, the first group of outputs of the error decoder is connected to the second inputs of the corrector, and the second The output group is connected to the input of the OR element, the output of which is the signal “device failure”.

The disadvantage of this device is the low reliability of operation, since errors that occur simultaneously in information and control discharges are not corrected.

The aim of the invention is to increase the reliability of the device by correcting 94% of detected errors not exceeding the multiplicity of k-1, subject to the maximum detection of the number of errors in the code set.

This goal is achieved in that the device containing the original circuit, the encoding device, the scheme of the error syndrome, the decoder, the corrector, while the information inputs of the device are connected to the first inputs of the original circuit, the outputs of which are connected to the first inputs of the corrector, the outputs of the corrector are the outputs of the device, additionally contains the first to fifth elements AND, the first to eighth elements OR, the parity check circuit, inversion block, register, element NOT, address inputs, write input, read input, input "Reset", moreover, the information inputs of the device are connected to the first inputs of the first element And, the address inputs are connected to the second inputs of the original circuit and to the first inputs of the register, the recording input is connected to the third input of the original circuit, to the second input of the first element And to the second input of the register, the read input is connected to the fourth input of the original circuit, to the first input of the second element And, to the first input of the third element And, to the first input of the fourth element And to the third input of the register, the input "Reset" is connected to the fifth input of the original circuit and to the fourth input of the register, the outputs of the original circuit are connected to the second inputs of the second AND element, the outputs of which are connected to the first inputs of the first OR element, the second inputs of which are connected to the outputs of the first AND element, and the outputs are connected to the inputs of the parity circuit, to the inputs of the inversion block and to the first inputs of the encoder, the outputs of the parity check circuit are connected to the second input of the encoder, to the second inputs of the third AND element and to the fifth inputs of the register, the outputs of the inversion unit are connected to the third inputs m of the encoder, the outputs of the encoder are connected to the third inputs of the third AND element and to the sixth inputs of the register, the first inputs of the error syndrome circuit are connected to the outputs of the third AND element, the second inputs are connected to the outputs of the register, and the outputs are connected to the inputs of the decoder and the inputs of the second element OR, whose output is connected to the first input of the fifth AND element, the first group of decoder outputs is connected to the inputs of the third OR element, the second group of decoder outputs is connected to the inputs of the fourth IL element And, the third group of decoder outputs is connected to the inputs of the fifth OR element, the fourth group of decoder outputs is connected to the inputs of the sixth OR element, the fifth group of decoder outputs is connected to the inputs of the seventh OR element, the outputs from the third to sixth OR elements are connected respectively from the second to fifth inputs of the fourth of the AND element, and from the first to the fourth inputs of the eighth OR element, the output of the seventh OR element is connected to the fifth input of the eighth OR element, the output of which through the element is NOT connected to the second input of the fifth AND gate, the input of the fifth AND gate is the output device outputs the fourth AND gate connected to the second inputs of the corrector.

The drawing shows a block diagram of a device. The device contains the original circuit 1, the first element And 2, the second element And 3, the third element And 4, the fourth element And 5, the fifth element And 6, the first element OR 7, the second element OR 8, the third element OR 9, the fourth element OR 10 , fifth element OR 11, sixth element OR 12, seventh element OR 13, eighth element OR 14, encoder 15, error syndrome circuit 16, decoder 17, corrector 18, parity check circuit 19, inversion unit 20, register 21, element NOT 22, information inputs 23, address inputs 24, input 25 records, input 26 reads, input 27 reset, outputs 2 8 devices, output 29 "Device failure".

Information inputs 23 of the device are connected to the first inputs of the first element And 2 to the first inputs of the original circuit 1, the outputs of which are connected to the first inputs of the corrector 18, the address inputs 24 are connected to the second inputs of the original circuit 1 and to the first inputs of the register 21, the input 25 of the record is connected to the third input of the original circuit 1, to the second input of the first And 2 element and to the second input of the register 21, the read input 26 is connected to the fourth input of the original circuit 1, to the first input of the second And 3 element, to the first input of the third And 4 element, to the first input a quarter of the second element And 5 and to the third input of the register 21, the input 27 "Reset" is connected to the fifth input of the original circuit 1 and the fourth input of the register 21, the outputs of the original circuit 1 are connected to the second inputs of the second element And 3, the outputs of which are connected to the first inputs of the first element OR 7, the second inputs of which are connected to the outputs of the first element And 2, and the outputs are connected to the inputs of the parity checking circuit 19, to the inputs of the inversion unit 20 and to the first inputs of the encoding device 15, the outputs of the parity checking circuit 19 are connected to the second input of the coding arrange 15, to the second inputs of the third element And 4 and to the fifth inputs of the register 21, the outputs of the inversion unit 20 are connected to the third inputs of the encoder 15, the outputs of the encoder 15 are connected to the third inputs of the third element And 4 and to the sixth inputs of the register 21, the first inputs schemes 16 of the error syndromes are connected to the outputs of the third element And 4, the second inputs are connected to the outputs of the register 21, and the outputs are connected to the inputs of the decoder 17 and to the inputs of the second element OR 8, the output of which is connected to the first input of the fifth element And 6, the first group The decoder 17 is connected to the inputs of the third element OR 9, the second group of outputs of the decoder 17 is connected to the inputs of the fourth element OR 10, the third group of outputs of the decoder 17 is connected to the inputs of the fifth element OR 11, the fourth group of outputs of the decoder 17 is connected to the inputs of the sixth element OR 12, the fifth group of outputs of the decoder 17 is connected to the inputs of the seventh element OR 13, the outputs from the third 9 to the sixth 12 elements OR are connected respectively from the second to fifth inputs of the fourth element And 5 and the first to fourth inputs are eighth about element 14 OR, the output of the seventh element OR 13 is connected to the fifth input of the eighth element OR 14, the output of which through element NOT 21 is connected to the second input of the fifth element And 6, the input of the fifth element And 6 is the output of the device, the outputs of the fourth element And 5 are connected to the second inputs of the corrector 18.

The parity check circuit 19 is intended to generate a parity check digit value with respect to direct and inverse values of information bits.

Block 20 inversion is designed to invert the values of the information bits coming from the outputs of the first element OR 7, respectively, when writing and reading information.

In the encoding device 15, information bits and a parity bit are represented as a two-line information matrix:

r_ЧЕТ,

- соответственно прямые и обратные значения i-го информационного разряда и значения разряда четности кодового набора.where _i

r _EVEN

- respectively, direct and inverse values of the i-th information bit and the values of the parity bit of the code set.

Regarding the formed matrix in the encoder 15, right and left diagonal checks are performed.

The number of diagonal checks is determined by the formula:

R _D = 2 (k + 2).

When reading information, the encoder 15 generates (in the same way) a vector of check bits R ^{P of the} received code set.

Thus, during the period of writing and reading information at the output of the encoding device 15, we have, respectively, the vectors of the control bits:

R = r ₁ r ₂ ......................................., r _{2 (k +2)} ,

R ^P = r ₁ ^P r ^P .................................... r ^P _{2 (k + 2)} .

Scheme 16 of the error syndrome is intended for bitwise comparison of the values of the control bits obtained during the transmission of the code set and generated relative to the received values of the information bits and the direct and inverse values of the control bits of parity. It represents a set of adders with mod 2 (by the number of control bits - the number of diagonal matrix checks and one parity bit).

The result of adding, according to mod 2, the signal values of the transmitted and generated control bits will give an error syndrome:

E = e ₁ e ₂ e ₃ ........... e _{2 (k + 2)} e _EVEN e _EVEN .

The decoder 17 contains 2k + 6 inputs (the number of bits of the error syndrome) and L = l ₁ + l ₂ outputs (according to the number of matching circuits, which are 2k + 6 - input circuits And), where

- l ₁ - group of elements And (for various syndromes that characterize errors only in the control bits);

- l ₂ - group of elements And (for syndromes characterizing errors that occur simultaneously in the information and control bits).

In the event of errors at one of its outputs, a single signal is generated.

The outputs of the decoder 17 are combined into one output, respectively, using the third element OR 9, the fourth element OR 10, the fifth element OR 11, the sixth (k-th) element OR 12 for generating control signals for the corrector, respectively, for correcting the first, second ... k-th information bits.

The seventh element OR 13 combines the outputs of the decoder 17, (the outputs of the circuits And), belonging to the subset l ₁ and corresponding to the occurrence of errors only in the control bits (which do not require the formation of control signals to the corrector).

, возникающих на выходах исходной схемы 1. При исправлении ошибок реализуется функция относительно управляющих сигналов ui, поступающих с выходов элементов ИЛИ:The corrector 18 includes k elements of ambiguity and is designed to correct errors

arising at the outputs of the original circuit 1. When correcting errors, a function is implemented with respect to the control signals ui coming from the outputs of the OR elements:

The register 21 is designed to store the values of the signals of the vector of the control bits formed when recording information in the original circuit 1.

If errors occur that belong to a subset of n ₁ - for the same syndromes, indicating an error in different information bits (having the same value of the syndromes and additional checks, see the appendix), characterized by the presence of single values at the output of the circuit 16 error syndromes and the absence of single values at the outputs from the third 9 to the seventh 13 elements OR, using the second element OR 8, the eighth element OR 14, the element NOT 22, the fifth element AND 6, the signal ″ Device failure ″ is generated.

The device operates as follows. Before starting work, a signal is applied to input 27, which sets the device to its initial state. Upon receipt of the input information at the information inputs 23, the address inputs 24 and the signal ″ Record ″ to input 25, the information is recorded at the specified address in the original circuit 1. At the same time, it enters the inputs of the first element 2 AND, opened by the signal from input 25 and further through the OR 7, the input information is supplied to the first inputs of the encoding device 15, to the input of the parity check circuit 19, and to the inputs of the inversion unit 20. The second input of the encoding device 15 receives the value of the check bit for the parity of information bits, and the third inputs receive inverse values of the information bits. From the obtained parity bits, direct and inverse values of the information bits, a two-line information matrix is formed, with respect to which the right and left diagonal checks are organized in the encoding device 15, implemented on the adder group mod 2.

From the outputs of the encoder 15, the value of the vector of control bits is input to the register 21 and recorded at the specified address, which also records the direct and inverse values of the parity bit coming from the outputs of the parity check circuit 19.

When reading information at the specified address, the signals from the output of the original circuit 1, through the second element And 3, opened by the signal "Read" from input 26, the element OR 7 is repeatedly fed to the input of the encoding device 15, where the signal values are generated in the control bits relative to the information matrix, formed by the information received.

In this case, the information from the outputs of the encoder 15 through the third element And 4 enters the first inputs of the circuit 16 of the error syndrome, the second inputs of which receive information read from the register 21.

Scheme 16 of the error syndrome performs bitwise comparison of the values of the received control bits and formed relative to the received information.

As a result, at the output of the error syndrome circuit 16, we have the generated value of the error syndrome.

The decoder 17 when an error occurs generates a single signal at one of its outputs in accordance with the incoming value of the error syndrome. Depending on the number of the information category having an error, a control signal will appear at the output of the corresponding (9 ... 12) OR element. This signal through the open fourth element And 5 is fed to the input of the corrector 18, where the correction of erroneous information discharge occurs.

If an error occurred only in the control bits, the signal will appear at the output of the seventh element OR 13 (the supply of control signals to the corrector is not required).

The outputs of the decoder 17 are combined into one output, respectively, using the third element OR 9, the fourth element OR 10, the fifth element OR 11, the sixth (k-th) element OR 12 for generating control signals for the corrector, respectively, for correcting the first, second ... k-th information bits.

The seventh element OR 13 combines the outputs of the decoder 17 (the outputs of the circuits And), belonging to the subset l ₂ and corresponding to the occurrence of errors only in the control bits (which do not require the formation of control signals to the corrector).

, возникающих на выходах исходной схемы 1. При исправлении ошибок реализуется функция относительно управляющих сигналов ui, поступающих с выходов элементов ИЛИ:The corrector 18 includes k elements of ambiguity and is designed to correct errors

arising at the outputs of the original circuit 1. When correcting errors, a function is implemented with respect to the control signals ui coming from the outputs of the OR elements:

If errors belonging Subset n ₁ - for identical syndromes, indicating an error in the various information bits (having the same value syndromes and additional checks, see app.), Characterized by the presence of single values at the output of circuit 16 the syndromes of errors and the absence of single values at the outputs from the third 9 to the seventh 13 elements OR, using the second element OR 8, the eighth element OR 14, the element NOT 21, the fifth element AND 6, the signal ″ Device failure ″ is generated.

application

Correction of errors of a given multiplicity, provided that errors are detected in the remaining bits of information, can be achieved based on an iterative code.

The procedure for constructing a two-dimensional iterative code is as follows [3]. A given set of information symbols is divided into groups (blocks, modules) of information, by b-bits in each group. The resulting information modules are presented in the form of an information matrix (1):

Then the information is encoded using the parity method (by adding mod 2 characters of rows and columns of the resulting matrix). As a result, we have a two-dimensional iterative code that allows us to detect and correct any single error:

where H = h ₁ , h ₂ , ..., h _m is the line parity vector; Z = z ₁ , z ₂ , ..., z _b is the column parity vector. The parity vectors of rows and columns form the set of control bits R ₁ = {r ₁ , r ₂ , r _m , r _{m + 1} , ..., r _b }. Upon receipt of the code combination relative to the information bits, the values of the control bits R ₁ ^P = {r ₁ , r ₂ , r _m , r _{m + 1} , ..., r _b } are re-formed. In this case, the difference between the transmitted values of the control bits and received after receiving the information forms the error syndrome E:

In this case, the bits of the error syndrome e ₁ e ₂ ... e _m (obtained with respect to the row parity vector) indicate the module of information that has an error, and the bits e _m e _{m + 1} ... e _b (obtained with respect to the column parity vector) indicate erroneous bit in the information module.

Since code combinations of rows and columns have a minimum distance d = 2, the minimum distance of this code is d = 4. This code allows you to correct any single error and detect a significant proportion of multiple errors.

The structures of errors not detected by the two-dimensional iterative code are shown in the figure:

Fig. 1 Structures of errors not detected by a two-dimensional iterative code: a) errors of multiplicity 4; b) - errors of multiplicity 6.

Fig.2 Error structures of a two-dimensional iterative code, leading to erroneous correction: a) errors of multiplicity 5; b) - errors of multiplicity 7.

In the general case, iterative codes of higher dimension can be constructed (three-dimensional, four-dimensional, etc.), where each information symbol will be a component of x different codewords at the same time. The parameters of iterative codes of dimension x are as follows [3]:

where n _i , k _i , d _i are the length, the number of information bits, the minimum distance of the code sets of rows and columns, respectively.

Based on this, to build iterative codes should use checks that have the highest detecting ability.

Thus, the organization of diagonal checks of the matrix under consideration will allow us to identify error structures that are not detected by an iterative code that implements parity checks of rows and columns.

The structure of diagonal checks that detect the considered errors has the form shown in Fig. 3.

Left diagonal checks are formed according to the rule:

The results of the right diagonal checks are formed by summing the values of the following information bits:

In this case, the total number of diagonal checks is 2l, or

Example 1. Let the word in question consists of four information bits that have zero meanings. For this code set, the information matrix has the form:

In this case, checks for the parity of rows and columns of the information matrix will give zero values, and in addition, the results of all right and left diagonal checks will have zero values. If an error occurs in all information bits, we have an even error that cannot be detected by a two-dimensional iterative code, because parity checks of rows and columns of the information matrix have zero values:

At the same time, the right and left diagonal checks will give a result of 101.

Proposition 1. An iterative code that implements right and left diagonal checks detects all even errors that are not detected by the two-dimensional iterative code, and identifies odd errors that are perceived by the two-dimensional iterative code as correctable.

In turn, there are error structures that are not detected by iterative code that implements right and left diagonal checks and checks for the parity of rows and columns. The structures of the considered errors are presented in Fig. 4.

Fig. 4 Structures of errors not detected by diagonal checks and checks of rows and columns.

So, for example, with respect to the information matrix having zero values, the following error structure will not be detected by diagonal checks.

In order to exclude the appearance of the considered errors, the information matrix should contain no more than two rows.

Proposition 2. For an information matrix b × 2, an iterative code that implements right and left diagonal checks detects the maximum number of possible errors (except for the set of 2 ^k -1 forbidden code sets that can be transformed into allowed code sets).

Thus, when using an iterative code that implements right and left diagonal checks and parity checks, the code set is transmitted in the form:

For this example, the encoding of information is as follows:

r ₁ = y ₁ ; r ₂ = y ₂ ⊕y ₃ ; r ₃ = y ₄ ; r ₄ = y ₃ ; r ₅ = y ₁ ⊕y ₄ ; r ₆ = y ₂ .

The result of adding the values of the signals of the control bits transmitted and received will give an error syndrome:

where the bits of the error vector r ₁ , r ₂ , ......... r _2l - correspond to the right diagonal checks, r _l , r _{l + 1} ......... r _2l - to the left and formed relative to received information bits;

- значения полученных контрольных разрядов.

- the values of the received control bits.

Property 1. There are such error configurations in information and control bits for which the error syndromes have the same meanings.

To distinguish these errors during the formation of error syndrome values, additional diagonal checks are organized:

Thus, each error from the set of errors M = (2 ⁿ ) k can be associated with the value of the error syndrome and the value of additional diagonal checks.

Property 2. Each set of values of the error syndrome and the value of additional checks corresponds to a subset of Q-errors of various configurations.

Corollary 1. To distinguish between errors belonging to this subset, it is necessary to limit the multiplicity of correctable errors and increase the number of control bits (perform additional coding of information bits).

In this regard, the proposed encoding method includes the following provisions:

1) in order to ensure the correction of 94% of errors that occur, it is advisable to limit itself to correcting errors whose multiplicity does not exceed k-1;

2) checks for the parity of information bits;

3) from direct inverse values of information bits and

values (direct and inverse) parity discharge is formed by the information matrix:

4) for the obtained information matrix, right and left diagonal checks are organized. The number of diagonal checks (the number of control bits) is determined by the formula:

5) the code set is transmitted in the form:

6) the result of adding the signal values of the transmitted and generated control bits will give an error syndrome:

7) when the error syndrome is formed with respect to the received and generated values of the control bits, additional diagonal checks are organized, the number of which is determined by the expression:

), характеризующихся определенными значением синдрома ошибки и дополнительной проверки;8) as a result, we have many errors of a given multiplicity (in this case, from single to multiplicity k-1, defined by the expression:

) characterized by a specific value of the error syndrome and additional verification;

9) the set N is divided into four subsets N = n ₁ + n ₂ + n ₃ + n ₄ , where

n ₁ - syndromes having the same additional checks (uncorrectable errors);

n ₂ is a subset of groups (each group includes 2 ^k- identical values of the syndromes) in the presence of errors only in information bits;

n ₃ - a subset of groups (each group includes 2 ^k- identical values of the syndromes) in the presence of errors only in the control bits;

n ₄ is a subset of groups (each group includes 2 ^k- identical values of the syndromes) in the presence of errors simultaneously in the information and control bits.

Note that for errors not exceeding the multiplicity k-1, there are no erroneous code sets that can be transformed into allowed (serviceable) code sets.

Based on the obtained coding rules, a decoding strategy is formed that solves the problem of distinguishing errors in information and control bits, and the rules for correcting errors that arise, which includes the following points:

1) identical additional checks are revealed, according to which error syndromes belonging to the subset n ₁ are excluded from the set N (uncorrectable errors are detected for which the "Device failure" signal is generated);

2) groups of identical syndromes (indicating an error in the corresponding information bits) are determined for the subset n ₂ ;

3) groups of error syndromes belonging to a subset of n _{3 are} determined for which correction of information bits is not required;

4) groups of the same values of the error syndromes belonging to the subset n ₄ and that allow correcting errors in the corresponding information bits are revealed.

For the considered example that implements the proposed encoding method, we have:

- total number of errors - 15792;

- 960 - the number of identical error syndromes that have the same additional checks (subset n ₁ );

- 14832 - the number of correctable errors (94%);

- the number of errors only in information bits is 0;

- the number of errors only in the control categories is 7312 (l ₂ = 457 groups, each of which includes 16 identical syndromes);

- the number of errors having distortions simultaneously in the information and control bits is 7520 (l ₃ = 470 groups, each of which includes 16 identical syndromes).

Table 1 presents a part of the values of the error syndromes for the subsets n ₂ , n ₃ , n ₄ (excluded are the error syndromes of the subset n ₁ , which have the same values of additional checks).

Table 1. Mistake Inf. bit Accepted by the Kyrgyz Republic Formed. KR Syndrome y ₁ y ₂ y ₃ y ₄ r ₁ r ₂ r ₃ r ₄ r ₅ r ₆ r ₇ r ₈ r ₉ r ₁₀ r ₁ r ₂ r ₃ r ₄ r ₅ r ₆ r ₇ r ₈ r ₉ r ₁₀ e ₁ e ₂ e ₃ e ₄ e ₅ e ₆ e ₇ e ₈ e ₉ e ₁₀ Only in control 0101

000000100010 000000000001 0101

000000100010 100000000000 0101

000000100010 110000000000 0101

000000100010 000000000011 0101

000000100010 111000000000 0101

000000100010 000000000111 Information only

000101100111 000000100010 000101000101

110011010001 000000100010 110011110011

101000001010 000000100010 101000101000

001010101000 000000100010 001010001010

101101001111 000000100010 101101101101

111001011011 000000100010 111001111001 And in the control, and in the information

000000100010 010011110011

000000100010 110011110010

000000100010 100101000101

000000100010 111000101000

000000100010 011100111100

000000100010 000101000110

The proposed encoding method allows you to:

Correct an error of a given multiplicity;

detect the maximum number of errors (with the exception of erroneous code sets that are transformed into allowed code sets);

signal a malfunction of the memory device when an uncorrectable error occurs.

Information sources

1. Scherbakov N.S. The reliability of digital devices. M.: Engineering, 1989, 224 p., Fig. 39, Fig. 44.

2. A positive decision on the application (21) 99111190/09 dated 01/15/03 (filed May 31, 09), authors: Tsarkov AN, Bezrodny B.Yu., Novikov NN, Romanenko Yu.A., Pavlov A.A.

3. Khetagurov Ya.A., Rudnev Yu.P. Improving the reliability of digital devices using redundant coding methods. M .: Energy, 1974, 270 p.

Claims (1)

A fault-tolerant information storage device containing a memory device, an encoding device designed for performing right and left diagonal checks and forming a vector of control bits, an error syndrome diagram, a decoder, and a corrector designed to correct errors that occur at the outputs of the memory device, the information inputs of the device are connected to the first inputs of the storage device, the outputs of which are connected to the first inputs of the corrector, the outputs of the corrector are the outputs and a device, characterized in that it additionally contains from the first to fourth group of AND elements, the fifth AND element, the OR group of elements, the second to eighth OR elements, the parity check circuit, the inversion unit, the register, the NOT element, address inputs, the input write, read input, input "Reset", and the information inputs of the device are connected to the first inputs of the elements And the first group, the address inputs are connected to the second inputs of the storage device and to the first inputs of the register, the write input is connected to the third input of the storage device triads, to the second inputs of the AND elements of the first group and to the second input of the register, the read input is connected to the fourth input of the storage device, to the first inputs of the elements AND of the second group, to the first inputs of the elements AND of the third group, to the first inputs of the elements AND of the fourth group and the third the input of the register, the input "Reset" is connected to the fifth input of the storage device and to the fourth input of the register, the outputs of the storage device are connected to the second inputs of the elements AND of the second group, the outputs of which are connected to the first inputs of the first group UPP elements OR, the second inputs of which are connected to the outputs of the elements AND of the first group, and the outputs are connected to the inputs of the parity check circuit, to the inputs of the inversion unit and to the first inputs of the encoder, the outputs of the parity check circuit are connected to the second input of the encoder, to the second the inputs of the AND elements of the third group and the fifth inputs of the register, the outputs of the inversion unit are connected to the third inputs of the encoder, the outputs of the encoder are connected to the third inputs of the elements of the third group and to the sixth input m of the register, the first inputs of the error syndrome circuit are connected to the outputs of the AND elements of the third group, the second inputs are connected to the outputs of the register, and the outputs are connected to the inputs of the decoder and the inputs of the second OR element, the output of which is connected to the first input of the fifth AND element, the first group of decoder outputs connected to the inputs of the third OR element, the second group of decoder outputs connected to the inputs of the fourth OR element, the third group of decoder outputs connected to the inputs of the fifth OR element, fourth group of decoder outputs connected to the inputs of the sixth OR element, the fifth group of decoder outputs connected to the inputs of the seventh OR element, the outputs from the third to sixth elements OR connected to the second inputs of the AND elements of the fourth group and the first to fourth inputs of the eighth OR element, the output of the seventh OR element connected to the fifth the input of the eighth OR element, the output of which through the element is NOT connected to the second input of the fifth AND element, the output of the fifth element AND is the output “Device Failure”, the outputs of the And elements of the fourth group are connected to the second odes corrector.