SU938284A1 - Device for processing numbers on bit-by-bit basis - Google Patents

Description

The invention relates to computing, namely multiprocessor computing systems. A device for sequential processing of t1 numbers is known. A disadvantage of the known device is the inability to handle the numbers represented in the form of a floating point number. The closest technical solution to the invention is a computing device containing a storage unit, a shift node, shift registers, random access memory, a normalization node, processors consisting of shift registers, switches, arithmetic-logical processing nodes, a sign unit, the outputs of the operative storage device are connected to the first and second inputs of the processors, and the outputs of the processors are connected to the corresponding inputs of the operational storage device t2. A disadvantage of the known device is the low performance due to the fact that the known device cannot directly process the numbers represented in the form of a floating point. The purpose of the invention is to expand the functional capabilities and increase productivity. This goal is achieved by the fact that in a device for bit-by-bit processing of numbers represented in the form of a floating point number containing N processors, each of which contains four switches, four arithmetic-J blocks, an encoder, seven shift registers and a sign shaper, and also common for all processors are two memory blocks, two switching nodes and m shift registers, whose outputs are combined and connected to the control input of the second memory block, whose data input is connected to the processor outputs, the output of the second block PA The mi are connected to the first and second inputs of each processor, the information input of the first memory block is connected to the input input of the device, the third inputs of each processor are combined and connected to the input of the operation code of the device, the inputs of the Shift registers m are interconnected and connected to the output of the node com the mutations, the input of which is connected to the output of the first memory block, the input of which is connected to the output of the second switching node, whose input is connected to the output of the second memory block, and in each processor the output of the first switch connects The first, second, third and fourth inputs of the switch are connected to the output of the sign maker, the output of the first arithmetic unit, the output of the second arithmetic unit, the output of the first shift register and the input of the second shift register, respectively, the output of which is connected to the first information input of the first arithmetic -logical block, the second information input of which is connected to the information input of the sign maker, the first information input of the second arithmetic of the cological unit and the first The third output of the arithmetic logic unit, the second output of which is connected to the input of the first shift register, the first information input of the third arithmetic logic unit connected to the output of the second switch, and the second information input to the output of the third switch, the control inputs of the second, third and the fourth switches are combined and connected to the output of the fourth arithmetic logic unit, the first information input of which is connected to the first input of the encoder, the input of the third shift register, the input four the shift register, the first information input of the second switch and connected to the first processor input, the output of the third shift register is connected to the second information input of the second switch, the first information input of the third switch is connected to the input of the fifth shift register, the second information input of the fourth shift register, the second input encoder and connected to the second input of the processor, the output of the encoder is connected to the control inputs of the first, second and third arithmetic logic unit and driver nak, the output of the fifth shift register is connected to the second -: information input of the third switch; the outputs of the fourth and sixth shift registers are connected to the first and second information inputs of the fourth switch, respectively, the output of which is connected to the input of the seventh shift register, the output of which is connected to the second information input of the second arithmetic logic unit. The first arithmetic logic unit contains the element AND, the adder, two triggers, the element NOT and the switch whose output is connected to the output of the block. The first information input of the switch is connected to the input of the element and the information output of the adder, the transfer output of which is connected to the transfer input of the adder , the first information input of which is connected to the first information input of the block, the second information and control inputs of the block are connected to the first and second inputs of the And element, respectively, the output of which is connected to the second m data input of the adder and vhodom.vtorogo trigger whose output is connected to the control input of the switch, a second data input connected to the output of NOT circuit. The second arithmetic logic unit contains an OR element, an adder and a trigger, the output of which is connected to the transfer input of the adder, the first information input of which is connected to the output of the OR element, the first informational, second informational and control inputs of the block are connected to the first and second inputs of the OR element and the second information input of the adder, respectively, the transfer output of the adder is connected to the trigger input, the output of the sum of the adder is connected to the output of the block. The third arithmetic logic unit contains the element NOT, the switch, the adder, the trigger, the first and second elements AND, the outputs of which are connected to the first and second inputs of the block respectively, the first information input of the block is connected to the first information input of the switch and the input of the element NOT whose output is connected With the second information input of the switch, the control input of which is connected to the second information input of the block and the first inputs of the first and second elements And, respectively, the second inputs are combined under The switches are connected to the trigger output and the transfer input of the adder, the output of which is connected to the trigger input, the first information input of the adder is connected to the output of the switch, and the second information input of the adder is connected to the control input of the block. The fourth arithmetic logic unit contains four elements NOT, two. adder, two triggers, two shift registers, switch, two elements OR, two elements AND, a block of elements NOT, a block of elements AND, and a block of elements NAND, the output of which is connected to the first inputs of the first and second elements AND, the second input of the first element AND is connected to the first input of the first element OR and the output of the first element NOT, the output of which is connected to the output of the first trigger and the transfer input of the first adder, the transfer output of which is connected to the Trigger Input, and the information output to the input of the first shift register o connected to, the first input of the switch, the second input of which is connected to the output of the second shift register, the input of which is connected to the information output of the second adder, the transfer output of which is connected to the input of the second trigger, the output of which is connected to the input of the second element and the transfer input of the second adder , the first information input of which is connected to the output of the third element NOT, the input of which is connected to the first information input of the AND block, the First information input of the first adder, the second information input in which is connected to the output of the fourth element NOT, the input of which is connected to the second information input of the block and the second information input of the second adder, the output of the switch is connected to the input of the block of elements NOT, the output of which is connected to the input of the block of elements AND-NOT and the input of the block of elements AND, the output of which is connected to the second input of the first element OR and the first input of the second element OR, the output of the second element is NOT connected to the third input of the switch, the second inputs of the second element AND and the second element OR, and the output of the block, the outputs of the first and second elements And connected to the output of the block. FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a diagram of the node 2 switching; in fig. 3 is a diagram of the node 3 switching; in fig. 4 is a diagram of the arithmetic logic unit 18; in fig. 5 is a diagram of the arithmetic logic unit 19; Fig 6 is a diagram of the arithmetic logic unit 20; in fig. 7 is a diagram of an arithmetic logic unit 21. A device for bit-by-bit processing of numbers represented in floating point form contains a memory block 1, a switching node 2 for controlling the shift, a shift register 3 a memory block, a switching node 5 intended for normalization, and processors 6, each of which consists of shift registers 7-13, switches of arithmetic logic units 18-21, encoder 22, sign maker 23 Switch node 2, contains switches 2C, forming the first Russian, and switches 25, forming second rus. The connection of the bit buses of the shifting chassis A (a)., With the inputs of the switches 2k and the outputs of the switches 2 with the inputs of the switches 25 is shown in Table. 1 and 2. The switching node 5 contains elements HE 26, the inputs of which are connected to twelve higher bits of the normalized number, and the outputs of elements HE 26 are connected to the inputs of elements AND 27, the outputs of which are connected to the inputs of elements HE 28. The output of the first element And 27, besides, it is connected to the first inputs of elements AND 29-31- The output of the second element AND 27 is also connected to the second inputs of elements AND 30 and 31, and the output of the third element And 27 is also connected to the third input of element And 31 The outputs of the second and third elements are NOT 28 connected to the second and third in s, respectively, AND gates 29 and 30. The outputs of the first member 28 and NOT outputs of AND gates 29-31 are connected to inputs of the encoder 32, the outputs of which are connected with the control inputs of switches 33 constituting the first switching node 5 rus. The outputs of the first three switches 33 of the first Rus are connected to the inputs of cells NOT W, the output of the first of which is connected to the first inputs of the AND elements, the output of the second to the second inputs of the I & 3 elements and 37 and the output of the third to the third input of the I elements 37. The outputs of the second and the third switch 33 is also connected respectively to the second input of the element 35 and to the third input of the element 36, the output of the first switch 33 and the outputs of the elements I are connected to the inputs of the encoder 33, the outputs of which are connected to the control inputs of the switches 39, said second switching node 5 rus. The connection of the discharge buses of the normalized number of C / s, s ,, ..., s- / with the inputs of the switches 33 and the outputs of the switches 33 with the inputs of the switches 39 is shown in Table. 3 "The arithmetic logic unit 18 includes the HE 40 elements, the adders I, triggers, the HE elements 43 shift registers kk, the switch, the A6 block of the NOT elements, the block of the 7 elements AND, the block of the NAND elements, the elements OR k3 and elements 50. The arithmetic logic unit 19 includes the HE element 51, the switch 52, the adder 53 trigger 5, the And elements 55. The arithmetic logic block 20 includes the element OR 56, the sum of the torus 57 and the trigger 5B. The arithmetic logic unit 21 includes an adder 59, a trigger 60, a switch 61, a HE element 62 a trigger 63, an AND 64 element. The operation of the encoder 22 is determined by the table. k. The functioning of the sign maker is in accordance with the table. 5. The device operates as follows. Let us describe the operation of the computer system by the example of operations of the type Compound subtraction. The numbers in memory block 1 are stored in floating point form. One bit is placed under the sign of the number, the bits are the same as his sign, the bits are under the mantis. For processing in processors 6, these numbers are converted into the following formula. From the n bits of the order G is distinguished ((most significant bits so that fi 0. (where | A | is the integral part of A.) The content of the selected h, bits will be called an octave. The number mantissa should be shifted to the left by the number bits, corresponding to the binary number stored in the remaining younger "- n, bits of the order. This conversion of the original information occurs in node 2, hence the number containing one sign bit-r d, n, j bits octave and.) bits of the mantissa, is transferred to one of the shift registers 3. After filling all the shift registers 3, shifts begin in the latter. The outgoing bits of the same name from registers 3 are written cell by cell into memory block k. Information conversion cycles in node 2 and writing it into shift registers 3 followed by rewriting into memory block k are repeated until until all the information is needed is in the memory block k. The processors 6 work as follows: From the control unit (not shown) all processors 6 receive the same operation code (A + B, AB, B-A, and t. P.). From the operative memory device, a cell is read, storing the characters of the source numbers that go to the first and second inputs of the corresponding processor 6, and from these inputs - to the encoder 22. In this site 22, the received operation code and the characters of the original numbers are analyzed and the control numbers are generated. signals with addition or subtraction). Then, from the memory block k, the cells storing the octaves of the initial numbers (starting with the least significant octaves) are read out one after the other. Each processor 6 receives the corresponding octaves, which nocTj are fed to the inputs of the arithmetic logic unit 18, where subtraction occurs. At the same time, the octave bits are pushed into the shift registers 11 and 12. As a result of the subtraction, signals are generated that indicate, first, which of the octaves more, this signal goes to the control input of the switch 17 in order to skip a large octave from the shift register 11 or 12 to the shift register 13. Secondly, signals are generated that indicate the equality of the octaves, the difference of the octaves, equal to one and more units.

From these signals in the same block, 18 control signals are generated for switches 1L and 15 simultaneously.

After the last block of memory from the memory block (the highest bit of the octaves came in each processor 6 to block 18, where the described processing occurred, reading of the mantissa begins (also from the lower bits j from block 4 of the Mantissa arrive at the inputs of the processors b and then) shift registers 7 and 8 having 2 bits. After filling the shift registers 7 and 8, the mantissa from block k continues to be read, but switches 1 and 15 now start working.

In case of equality of octaves, the information from the shift registers 7 and 8 passes through the switches 1 and 15. If the difference of octaves is one, the mantissa corresponding to the larger octave passes through the switches I or 15 from the shift register 7 or, respectively, 8, and the other mantissa passes through the switch 15 or Ik at the input connected to the input of processor 6. Thus, the mantiss is shifted by rows. If the difference in octaves is greater than one, one of the switches H or 15 passes through the mantissa corresponding to the greater octave, while the other switch 15 or I is closed.

Information from the outputs of the switches lit and 15 goes to the inputs of the arithmetic logic unit 19, where the control signals from the encoder 22 are added or subtracted by the control signals. In the latter case, the reverse code of one of the operands is also formed in block 19. The resulting number enters the shift register 9, and after filling it pushes the JU shift register 10. Signals are processed after the last (senior) bits of the mantissa in the arithmetic logic unit 19 indicating whether there was an overflow on addition or, on subtraction, on which code (direct or reverse) the result was obtained. In addition, a circuit (not shown) that triggers null information in shift register 9 is triggered.

The overflow signal from block 19 enters the sign shaper 23.

in which, based on the analysis of the characters of the initial numbers and the operation code (coming from the encoder 22), a result character is formed and then transmitted through the switch 16 for recording in the memory block k.

The same overflow signal enters the arithmetic logic unit 20. If in this processor 6 an addition operation is performed, if the overflow signal is equal in block 20, the unit is added to the larger octave of the shear register 13 in block 20. The resulting octave from block 20, through switch 16 is transmitted for recording to block 4 of memory. If, as a result of adding mantissas in shift register 9, zero information is received, the specified scheme will work to detect this fact (not shown) and, according to its signal in block 20, one unit will be subtracted from the octave from the shift register 13 In the remaining cases (t i. when adding without overfilling, when subtracting, the octave from the shift register 13 passes without changing through the arithmetic unit 20.

After the transfer of the resulting octave through the switch 16 has finished, the processing of the number stored in the shift registers 9 and 10 begins. If the addition of the mantissa overflow signal generated in the arithmetic logic unit 19 is equal to zero, the resulting mantissa from the shift registers 9 and 10 is transmitted sequentially bit by bit without changing through block 21 and then through switch 16 to memory block k. If this overflow signal is equal to one, a part of the mantissa from the shift register 9 is transferred to the memory block k directly through the switch 16, and the block 21 mines. Thus, the mantissa is normalized to the right by 2 1 1-bits, with a preliminary addition of one to octave of this result. The shift register 9 has 2 Centers, and after the contents of this register 9 are transmitted through the switch 16, zeros are written to the upper bits of the resulting mantissa. This is achieved by blocking the switch 1b by the action of the overflow signal and the addition signal (not shown. In the case of subtracting the mantis, the overflow signal from block 19 is cyclic transfer. This signal goes to the arithmetic logic unit 21, where it is added to the mantissa coming from shift registers 10 and 9. The same cyclic transfer signal determines in which code (forward or reverse) the result is output from block 21 to switch 16. Calculations in processors 6 are organized along a conveyor principle. An odd pair of source numbers begins to flow into processor 6 immediately at $ 1 as soon as the last bit of the previous input numbers enters it. Similarly, the output of processor 6 generates one processing result after another. Synchronization of the work of the component parts of processors 6 is performed by a common temporary strobe MIs from the control device and the delay triggers entering the nodes of each processor are not shown). When performing logical operations on the initial numbers, the information from the memory block is fed to the inputs of the shift registers 7 and 8. Then, it is transmitted through the switches I and 15 to the arithmetic logic unit, where the necessary logical processing is performed. The resulting chip through the shift registers 9 and 10 and block 21 is transmitted to the switch 16 and through it further to the output of the processor 6. From the described example of the operation of the computing system, it is seen how time savings are achieved with

(ich-); - (: 12 information processing. Conversion of numbers represented in the floating-point form, carried out in node 2 and in shift registers 3, simplifies the computational process over numbers, namely, remove two very complicated order alignment procedures :( and the associated shift of one of the mantis and normalization of the result with the correction of the resulting order. The difficulty of these procedures is associated with the different time expenditures for their implementation in different processors 6 due to the different shifts, which complicates the calculation synchronization process in all processors 6. The form of representation of numbers adopted in the proposed computing system allows not only to speed up the calculations, but also to simplify the algorithms for performing operations so that all microoperations are the same for all processors 6. Thus, it is possible to remove local control in processors 6 and control the common for all control devices (not shown). It should also be noted that the exchange of information between the memory unit 1 and the memory unit does not require additional time and can occur simultaneously with the operation of the random access memory k with processors 6. While some areas of the memory unit t are busy working with processors 6, other areas This block j can exchange information with memory block 1. Table 1

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Claims (3)

Prev Table. LABLE 5 Invention 1. A device for bit-by-bit processing of numbers represented in the floating-point form, containing N processors, each of which contains four switches, four arithmetic logic units, an encoder, seven shift registers and a sign conditioner, as well as all processors, two memory blocks, two switching nodes and t shift registers, whose outputs are combined and connected to the control input of the second memory block whose data input is connected to the processor outputs, the output of the second memory block connected to the first and second inputs of each processor, the information input of the first memory block is connected to the input of the device, the third inputs of each processor are combined and connected to the input of the operation code of the device, characterized in that, in order to increase performance, the inputs of the shift registers are interconnected and connected to the output of the first switching node whose input is connected to the output of the first memory block whose input is connected to the output of the second switching node whose input is connected to the output of the second block The memory, and in each processor, the output of the first switch is connected to the output of the processor, the first, second, third and fourth inputs of the switch are connected to the output of the sign maker, the output of the first arithmetic logic unit, the output of the second arithmetic logic unit, the output of the first shift register and the input of the second shift register, respectively, the output of which is connected to the first information by the on-input input of the first arithmetic logic unit, the second information input of which is connected to the information input of the driver the first information input of the second arithmetic logic unit and the first output of the third arithmetic logic unit, the second output of which is connected to the input of the first shift register, the first information input of the third arithmetic logic unit connected to the output of the second switch, and the second information input to the output the third switch, the control inputs of the second, third and fourth switches are combined and connected to the output of the fourth arithmetic logic unit, the first information input of which is connected to the first input of the encoder, the input of the third shift register, the input of the fourth shift register, the first information input of the second switch and connected to the first input of the processor, the output of the third shift register connected to the second information input of the second switch, the first information input of the third switch connected to the input of the fifth the shift register, the second information input of the fourth arithmetic logic unit, the input of the sixth shift register, the second input of the encoder and is connected to the second input n the processor, the output of the encoder is connected to the control inputs of the first, second and third arithmetic logic unit and the sign maker, the output of the fifth shift register is connected to the second information input of the third switch, the outputs of the fourth and sixth shift registers are connected to the first and second information inputs of the fourth switch respectively, the output of which is connected to the input of the seventh shift register, the output of which is connected to the second information input of the second arithmetic logic unit, 2. The device according to claim 1, whether or not it is the fact that the first arifcho the methycological unit contains the element I, the adder, two T1 hggers, the element NOT and the switch whose output is connected to the output of the block, the first information input of the switch is connected to the input of the element NO and the information output of the adder whose transfer output is connected to the output of the first trigger connected to the transfer input of the adder, the first information input of which is connected to the first information input of the block, the second input (the information and control inputs of the block are connected to the first and second inputs of the AND element, respectively The output of which is connected to the second information input of the adder and the input of the second trigger, the output of which is connected to the control input of the switch, the second information input of which is connected to the output of the element HE. 3. The device according to claim 1, 1 and 2, is that the second arithmetic logic unit contains an OR element, an adder and a trigger, the output of which is connected to the transfer input of the adder, the first information input of which is connected to the output of the OR element, 40 The second, information and control inputs of the block are connected to the first and second inputs of the OR element and the second information input of the adder, respectively, the transfer output of the adder is connected to the trigger input, the output of the sum of the adder is connected to the output of the block. . A device according to claim 1, in which the third arithmetic logic unit contains the element NOT, the switch, the adder, the trigger and the first and second elements And whose outputs are connected to the first and second blocks, respectively, but the first the information input of the block is connected to the first information input of the switch and the input of the element NOT, the output of which is connected to the second information input of the switch, the control input of which is connected to the second information input of the block and the first inputs of the first and second elements AND, respectively but, the second inputs of which are combined and connected to the trigger output and the transfer input of the adder, the output of which is connected to the trigger input, the first information mutator, and the second information input of the adder - with the control input of the block. 5. The device according to claim 1, which means that the fourth arithmetic logic unit contains four elements NOT, two adders, two triggers, two shift registers, a switch, two OR elements, two AND elements , a block of elements NOT, a block of elements AND, and a block of elements AND-NOT, the output of which is connected to the first inputs of the first and second elements AND, the second input of the first element AND connected to the first input of the first element OR and the output of the first element NOT whose input is connected to the output the first trigger and the transfer input of the first adder, the output ne the transfer of which is connected to the trigger input, and the information output to the input of the first shift register, the output of which is connected to the first input of the switch, the second input of which is connected to the output of the second shift register, the input of which is connected to the information output of the second adder, the transfer output of which is connected to the input the second trigger, the output of which is soy by the transfer input of the second adder, the first information input of which is connected to the output of the third element NOT, the input of which is connected to the input of the adder is connected to the output the house is connected to the input of the second element NOT by the information input of the block and the first information input of the first adder, the second information input of which is connected to the output of the fourth element NOT, the input of which is connected to the second information input of the block and the second information input of the second adder, the output of the switch is connected to the input of the block of elements NOT, the output of which is connected to the input of the block of elements AND-NOT and the input of the block of elements AND, the output of which is connected to the second input of the first element OR and the first input of the second ele ment or. the output of the second element is NOT connected с2593 by the third input of the switch, the second inputs of the second element AND and the second element OR and the output of the block, the outputs of the first and second elements AND, the first and second elements OR are connected to the output of the block. Sources of information taken into account in the examination i 1.Parclnson B.D. DAPS add power to computer processing. - Electronics and instrumentation, NV, 1978, H 11. 2.Corsinl.P, and others. The serial microprocessorarry (SMA) Symp on comp arch, 5th, 1978, p. 230-235 prototype).  " " ё 5J sg "41 OS AND - oS. to - " - four E L I 5f / v / v r T Is T four ft I  NtftfMC loop LA f9 Mi 59 f ISO L4 61 - 5Z J 7