SU1283746A1 - Calculating device - Google Patents

Abstract

The invention relates to digital computing and is intended to perform elementary operations on blurry variables. The purpose of the invention is to expand the functionality by performing operations on vague variables in various bases. The device contains a decoder, a comparison circuit, an adder, three multiplexer control inputs, an input for specifying the operation code, four multiplexers, a bus driver, a memory block, a scheduling input to the device input data bus, an output information bus for the device, two groups of elements NOT , bidirectional device information bus, address selector bus of one of the memory block registers, read / write enable input and function select input for bidirectional information bus, enable input Records for the input bus information. All elementary operations — inversion, conjunction, disjunction, implication — are executed in one cycle. It is expedient to use the device as a processor element in specialized processors focused on processing vague information when creating them on microprogrammable BIS complexes, I pcs. W

Description

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4 F

1128

The invention relates to digital computing and is intended for performing elementary operations — inversion, conjunction, disjunction, implication — over blurred variables on different bases and is intended for use in specialized processors for processing blurry information.

The aim of the invention is to expand the functionality of the device by performing operations on vague variables in various bases.

The drawing shows the functional diagram of the device.

The device contains a decoder. 1 comparison circuit 2, adder 3, input

4 control multiplexer input

5 tasks of the code of the operation to be performed, multiplexers 6-8, bus driver 9, memory block 10, input

11 readings, output information bus 12 devices, multiplexer 13, group of elements HE 14, input 15 of control multiplexer, group of-elements NE 16, input information line 17 of device, input 18 of multiplexer exclusion 18, bi-directional information bus 19, address bars 20- 23 selecting one of the device memory block registers, read / write enable input 24 for informational bidirectional bus function selection input 25 for informational bidirectional bus, write enable input 26 for input block information bus and a memory.

The device is designed to perform elementary operations on vague variables in different bases.

Vague variable is a variable that takes a value from the interval 0, l and serves to evaluate the truth of inaccurate or fuzzy statements. Over such variables, the following elementary operations are introduced (a, b - fuzzy variables: inversion of the conjunction MiN (a, b) or a ((0, a +

  V I / VX /

| + B-1), disjunctions (a, b) or {1 5 a + b); implication (-a, b) or a. in

(, 1, -a + b), or

, 1 S if a; 6b

0 if a b

or

B

if a i b if a b.

five

0

5 0 j

0

5 Q

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The functional purpose of the elements and blocks forming the device.

The decoder 1 is designed to convert the input signals: the output (s) of the comparison circuit 2; transfer output (PI) of the adder 3, input 4 of the multiplexer control device 8 (ib), operation code — input 5 specifying the code of the {F-F2) device operation to output signals: transfer input for the adder 3 (PO) -, constant ( CONST); control multiplexer 6 (SHO, UR1). It implements logical functions in accordance with the table. The designations of the input and output variables in the table correspond to the designations written in brackets after the signal name.

The comparison circuit 2 is designed to compare two 8-bit codes, the value at output C is if the code values at the first input are greater than at the second, and O is otherwise.

Adder 3 is designed to add 8-bit codes and a possible transfer signal to a lower bit (PO, see table) and output the sum and possible transfer signal to the high bit (P).

The 8-bit multiplexer 6 serves for switching to the output name of the device 12 and the input information bus of the memory block or a constant, or values from the output of the adder 3, multiplexer 7 and multiplexer 8. The eight bits of the first information input of the multiplexer are combined and connected to the second output i.e., if the first information input of the multiplexer is selected, then the output will be a constant consisting of either zeros or ones.

The 8-bit multiplexer 7 is designed for switching to the inputs of the comparison circuit 2, adder 3, multiplexer 6, a direct or inverse value from the output of the multiplexer 13.

The 8-bit multiplexer 8 is intended for switching to the inputs of the comparison circuit 2, adder 3, multiplexer 6 of direct or inverse value from the second output information bus of the register block 10.

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The bus driver 9 provides the connection of the output bus 12 of the device to a common data line,

Memory unit 10 is a super-operative memory, containing four 8-bit registers and switching and control circuits, which allow reading data from any of the four registers on the output information buses, depending on the codes applied to the cooTBeTCTByromjie address inputs - pgins 20 and 21 and similarly recorded from the input information bus to any of the four registers depending on the code on bus 22. Recording is performed using a signal applied to input 26. A bidirectional information pin 19 can also be connected inputs or outputs of any of the four registers depending on the code applied to the bus 23. Read permission mode recording is determined depending on the signal applied to the input 25 and the entrance opening 24 is used to buffer circuits bidirectional data bus. Writing or reading to the register selected at the address provided to bus 23 is carried out only if the input level is active.

The 8-bit multiplexer 13 serves for switching to the inputs of the multiplexer 7 and a group of data inverters or from the input bus 17 of the device 20

25 l

H - - p

O

five

about

0

depending on the value of the control of its signal 18. b takes the values set on the second output information value of the memory block. The output information blocks of the memory block can be connected to the outputs of any of the four registers of the memory block, depending on the signals on pins 20 and 21. Thus, it can take values stored in any of the registers of the memory block or fed to the input information bus 17 of the device, which is controlled by the signal supplied to the gtin 20 and the input

mi

18 of the device, and b can take values stored in any of the registers of the memory block, which is controlled by the signals supplied to the bus 21 of the device.

Denote the multiplexer output

7a, multiplexer output 8 - b.

8 depending on the control signal 5 a can be either a or

inversions a, i.e. a, similarly, depending on the control sigia / 4 1jj-

la 4, b can take the value of b or b.

The operation node consists of a comparison circuit 2, an adder 3, a multiplexer 6 and a decoder 1. It is a combinational

scheme We denote the multiplexer / ra 6 -2. .

or from the first output information register 10 block.

In the proposed device, 8-bit codes are interpreted as unsigned 8-bit numbers with a dot fixed before the high-order binary bit, and the resolution is 1/256, the unit being represented by a code consisting of all ones.

The device can be divided into two main nodes - the storage and the formation of operands and the execution of operations.

The storage and operand node consists of a memory block 10, multiplexers 7, 8 and 13 and groups of inverters. Denote the output of the multiplexer 13a, the second output information bus of the memory unit 10 - b. At the same time, it may take values set on the input information value 17 of the device or

0

five

The commands executed by this node are presented in the table.

The table shows the following designations:

1. - the output of the multiplexer 7, the first data input of the operation execution node;

- the output of the multiplexer 8, the second data input of the operation execution node;

- output of the multiplexer 16, data output (result) of the operation node;

- command code;

- Comparison result 1.

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B

0 F., F.

F

WITH

five

 Oh j

if a

if a b

and yo; R - entry transfer to the younger

bit for adder 3j P - the output transfer in elder

bit 3 adder; CONST - constant O or 1 - output

decoder;

UR, UR, and .1 (in the table cell) control inputs of multiplexer 6;

control multiplexer 8 and the choice of constants.

about

x

active level of the corresponding signal; passive level, the value of the signal does not matter.

The device is designed to perform elementary operations on vague variables in one cycle, with its help it is possible to perform more complex operations, such as equivalence.

(a-ib) & {b-H a), but this requires three cycles of operation of the device, and the operations - and And can be any of the indicated. Consider the case when a-5 b in (1, 1 - a + b), a, (a ,, b).

Suppose that the operands are written in registers with the addresses 00 and O of the O-memory block, and the result must be output on the output time 12 "

Codes 00, 01 and 10 respectively are sent to the address inputs 20-22 of memory block 10, which mean that operands are taken from registers 00 in the first touch and written to iO, in addition to the memory block records are set to input 26 of the paspeDieHHH memory block level

The control input 18 of the multiplexer 13 is fed i, which ensures that its output transmits information from the first output information bus of the memory block 10.

The control inputs 15 and 4 of multiplexers 7 and 8 are respectively fed with signals 1 and О, which ensures the transmission of the inverted first operand and the non-inverted second, i.e. a -, b,

The input bus 5 of the operation code of the decoder receives the code 000, corresponding to the operation (1.8, + + b). Internal control signals arising from this are given in two rows of the table, corresponding to the operation (1, 8, + b),

The signals at input 1i, which control the output shaper 9s and input 24 of the iO memory block, must be inactive, and the values of the signals at inputs 19, 23, 25. and 17 are indifferent. At the end of ne

five

0

five

0

0

rehodnyh.protsessov in the schemes of the device at the output of the multiplexer

result of iplicapia min

/

8. And

And I 1

block II1 11

(IJ a + b)

b are respectively the contents of the memory register 00 and 01, this is the result recorded in the memory register O.

The second value of all input signals is the same, with the exception of the signals at the address inputs 20-22 of memory block 10, the following signals are then fed to the lean signals 01, 00, 11, which ensures that the operation is performed min (1, 1-аГ + b ) dNo here AG and b - the contents of the registers

P 1- f PPI

01, Oops, and the result is written to register P,

Codes 10 are supplied to address inputs 20 and 2 and 10 of memory. To the control input 18 of multiplexer 13, 1 is fed. To control inputs 15 and 4 of multiplexers 7 and 8, O is supplied, which provides a sample of non-inverted operands, i.e.

/ l- (™. - 1 t

a-a, b b. The active input is supplied to the control input 11 of the output bus drivers 9. At the inputs 5 of the operation code dep nfratora 1, the code 101 is received, corresponding to the operation L4MN Sz. , b), thus, at the output of multiplexer 6 and, consequently, on the output bus 12 of the device there will be mines (Te), where a, b are the contents of registers 10 and P.

So on. the first cycle performed the operation Pr (i, - (Pr 00) + + (Pr 01)), on the second Pr i 1 min (1.1- {Pr 0) + (Pr 00)), on the third output I mn ( (Pr 10), (WP 11)), i.e. In general, the operation Out (Pr 00) - - yy (Pr 0), where (WP 00) is the contents of register 00,

A device for performing elementary operations on vague

5 sets are intended for use as a processor section when building specialized computing devices for processing blurred information on

0 based on microprogrammed BIS systems. It is advisable to manufacture such a device in the form of a single LSI enclosure,

5 of the invention formula

A computing device containing a decipher, a comparison circuit, a memory block that distinguishes 5

so that, with the purpose of rasppyreny functionality due to the implementation of operations on vague variables in different bases, four multiplexers, two groups of NOT elements, an adder and a power driver have been introduced into it, and the device’s bi-directional information bus is connected to the bi-directional information bus of the memory block The first information output bus of which is connected to the first information input of the first multiplexer, the second information input of which is connected to the information input bus device, the first control input multiplexer which is connected to the control input of the first multiplexer, the output of which is connected to the first information input of the second multiplexer and the inputs of the elements of the first group, the outputs of which are connected to the second information input of the second multiplexer, the control input of which is connected to the second control multiplexer control input, the third control multiplexer control input of which is connected to the first

the input of the decoder and the control input bi-directional bus, the memory block, the second control input the memory block is connected to the input of the function selection for the information bidirectional pin of the memory block, the third control input of the memory block is connected by the write input for the input information bus of the memory block, the read input is connected to the control input of the bus driver, the output of which is the output of the device.

the house of the third multiplexer, the first information input of which is connected to the second information output bus of the memory unit and the inputs of the NOT elements of the second group, the outputs of which are connected to the second information input of the third multiplexer, the output of which is connected to the first inputs of the adder, the comparison circuit and the first information input of the fourth multiplexer second in

2837468

the formation input of which is connected to the output of the second multiplexer and the second inputs of the adder and comparison circuit, the output of which is connected to

5 second input of the decoder, the third input of which is connected to the transfer output of the adder, the output of the sum of which is connected to the third information input of the fourth multiplexer,

fO the output of which is connected to the information input of the bus driver and the input information bus of the memory block, the first, second, third and fourth inputs of which are connected to the address bus of selecting one of the device memory block registers, the input of setting the code of the performed operation of which is connected to the fourth , the fifth and sixth inputs of the decoder, the first output of which is connected to the transfer input of the adder, the second output of the decoder is connected to the fourth information input of the fourth multiplexer, the first and second

25 control inputs of which are connected to the third and fourth outputs of the decoder, the first control input of the memory unit is connected to the read / write enable input for information

The second control input of the memory unit is connected to the function selection input for the informational bi-directional memory of the memory unit, the third control input of the memory unit is connected to the write enable input for the input information bus of the memory unit, the read input is connected to the control input a tire driver, the output of which is the output of the device.

Pro chkgichr t, h niji-i

Claims (1)

Claim A computing device containing a decoder, a comparison circuit, a memory unit, characterized 7 in that, in order to expand functionality by implementing operations on vague variables in various bases, four multiplexers, two groups of NOT elements, an adder and a bus driver are introduced into it moreover, the bi-directional information bus of the device is connected to the bi-directional information bus of the memory unit, the first information output bus of which is connected to the first information input of the first a multiplexer, the second information input of which is connected to the input information bus of the device, the first control input of the multiplexer of which is connected to the control input of the first multiplexer, the output of which is connected to the first information input of the second multiplexer and the inputs of the elements of the NOT of the first group, the outputs of which are connected to the second information input of the second multiplexer the control input of which is connected to the second control input of the device multiplexer, the third control input of the multiplexer to is connected to the first input of the decoder and the control input of the third multiplexer, the first information input of which is connected to the second information output bus of the memory unit and the inputs of the elements of the second group, the outputs of which are connected to the second information input of the third multiplexer, the output of which is connected to the first inputs of the adder, circuit comparison and the first information input of the fourth multiplexer, the second information input of which is connected to the output of the second multiplexer and second inputs torus and comparison circuit, the output of which is connected to the 5th second input of the decoder, the third input of which is connected to the transfer output of the adder, the output of the sum of which is connected to the third information input of the fourth multiplexer, 10 the output of which is connected to the information input of the mud former and to the input information bus of the memory block , the first, second, third and fourth inputs of which are connected to address buses for selecting one of the registers of the device’s memory block, the input of setting the code of which operation is connected to the fourth, fifth and sixth inputs of the decoder 20, the first output of which is connected to the transfer input of the adder, the second output of the decoder is connected to the fourth information input of the fourth multiplexer, the first and second 25 control inputs of which are connected to the third and fourth outputs of the decoder, the first control input of the memory unit is connected with a read / write enable input for the bi-directional information bus. memory block, the second control input of the memory block is connected to the function selection input for bi-directional information of the memory block bus, the third control input of the memory block is connected to the write enable input for the input information bus of the memory block, the read input is connected to the control input of the mud block, the output of which is the output of the device. Function to be performed Decoder input Decoder output - ^F o ^s ' 1 R, willow RO CONST UR | Ivo ? "Missions (1, a + b ') 0 0 0 X 0 X 0 X 0 1 0 0 0 X 1 X 0 1 0 0 t = N «c (O, 'a' + £ + '-!) 0 0 1 X 0 X 1 0 0 0 0 0 1 X 1 X 1 X 0 1 r - ¹ 1 if a ί b 0 1 0 0 X X X 1 0 0 g - 0 if a> b 0 1 0 1 X X X 0 0 0 1283/46 llpoji. '' Π ”<- r η 5 · ι eggs h ί ^, ' ^ν '' ¹ ? -Mokc (a ₅ b) 10 0. 1 X X Υ X 1 0 2 = yanm (a ', b) ί o 1 0 X X X X 1 0 10 1 1 X X X X 1 1 Λ. 1 0 r = a eleven X X X X X 1 0 2 = 0 eleven 1 X X 0 X 0 0 0 r = 1 eleven 1 X X 1 X 1 0 0