SU1056206A1 - Device for implementing non-excessible aglorithm of fast fourier transform - Google Patents

Abstract

I. A DEVICE FOR RKALIZIZSH UNDERTAKING 1101 ALGORAGAL OF QUICK LOOR DISTRIBUTION, containing an arithmetic unit, a fixed memory unit, the first RAM unit and the control unit, the output of the first memory unit and the output of the memory card memory, and the output of the memory card memory, memory of the memory card, memory of the memory, memory of the memory, and the output of the memory memory and memory of the memory card memory. operands and goats input (}) 4) of the arithmetic unit's clients, the output of which is connected to the information input of the first RAM block, the first and second outputs of the control block are connected to the address inputs of the first opera block respectively, the third output of the control unit is connected to the write control input by reading the first RAM block, the fourth output of the control unit is connected to the sync input of the arithmetic unit, so as to speed up and expand fulkp The real capabilities of the device, which consists in calculating the compression simultaneously of up to four sequences of input samples, it contains a second block of RAM, and The second and sixth outputs of the control unit are connected respectively to the address input and the write control input of the second RAM memory unit, the seventh and eighth outputs of the control unit are connected to the access inputs of the first and second RAM blocks, respectively, the output of the second RAM memory unit is connected to the input of the operands of the arithmetic unit, and the control unit contains a synchronization node sync, two triggers, an n-bit counter (n log2N; N is the volume of you (B), (n + 1) -discharge register of iterations, node of elements AND, node of formation of inversion of code, element And of two subtractors, two (n + 1) -discharge ring register of shift and block of lock, the first output of the synchronization node is connected to the counting input of the first trigger, the output of which is connected to the counting input of the second trigger, the first input of the And element and to the information inputs of the first bits of the first and second ring shift registers, the second output of the second trigger is connected to the counter input, which subtracts the entrance of the first The reader also connects to the first input of the blocking node, the inverse of the output of the second trigger is connected to the subtracter (to its input of the second subtractor and to the second input of the blocking node, parallel output of the counter is connected to the first information input of the node of the I elements, to the information terminal input of the node of the formors;

Description

to the third input of the blocking node, the overflow output of the counter is connected to the shift control input of the iteration register, the parallel output of the iteration register is connected to the second information input of the And node, the output of the first bit of the iteration register is connected to the second input of the element The peak to the fourth input of the blocking node, the output (n + 1) of the iteration register bit is connected to the fifth input of the blocking node, the output of the inverse code formation node is connected to the summing inputs of the first and second Readers, whose outputs are bitwise connected to the information inputs of bits from the second to the (n + 1) -th first and second ring shift registers, respectively, the shift control inputs of the first and second ring shift registers, respectively, to the first and second outputs of the blocking node, outputs the second ring shift register, node H, the direct output of the second trigger, the second output of the synchronization node the output of the first ring shift register, the inverse output of the second three, third and fourth outputs uzp irovki are outputs of the control unit of the first through eighth respectively. T. The device according to claim 2, wherein the blocking node contains OR-NOT, OR, NOT elements, three modulators modulo two two AND-NOT elements, six AND elements and a trigger, and the element input is NOT the fourth input of the blocking node and connected to the first inputs of the first modulo-dw 06 and element lm, the second input of the first modulo-two adder is the fifth input of the blocking node, the inputs of the OR-NOT element from the first one appear corresponding to the third input of the node blocked ki, and the n-th input of the element OR is NOT connected to the inverse input of the trigger, the output of the element is NOT connected to the first inputs of the first and second elements AND-NOT, as well as the first and second elements AND, the output of the element OR is NOT connected to the second input of the element The SC, the output of which is connected to the first inputs of the third and fourth elements And, the second inputs of the third and fourth elements And are, respectively, the first and second inputs of the blocking node, the output of the third element And connected to the second input of the first element And and to the forward output - go elem The input And, the output of the fourth element And is connected to the second input of the second element And and to the direct input of the sixth element And, the inverse inputs of the fifth and sixth elements And are connected to the output of the first modulo-two adder, the outputs of the fifth and sixth elements And are respectively the third and fourth outputs of the blocking node, the direct and inverse outputs of the trigger are connected to the second inputs of the first and second elements AND-NOT, respectively, the outputs of the first and second elements AND-NOT connected to the first inputs of the second and third modulo adders the two, second inputs are connected to the outputs of the second and first elements AND, respectively, the outputs of the second and third modulo-two adders are the second and first outputs of the blocking node, respectively.

The invention relates to automation and computing and can be used to solve problems of spectral correlation processing of sequences of valid signals.

A device is known for realizing a fast Fourier transform,

containing the node reconfiguration of the counter, counter, register, group of elements OR and block, issuing addresses 1.

A disadvantage of the known device is the complexity of construction, low speed and the inability to form the addresses of the values of exponential factors stored in the permanent memory and intended for performing elementary FFT operations. In addition, without additional hardware costs, this device cannot implement the FFT algorithm with substitution. A device is known for implementing the Fast Fourier Transform algorithm, comprising fixed and main memory units, an arithmetic unit, and a control unit. The outputs of the fixed memory unit and the RAM unit are connected to the inputs of the arithmetic unit, the outputs of the control unit are connected to the control inputs of the permanent memory unit, the operational memory unit and the arithmetic unit 2. The disadvantages of the known device are the low efficiency of the arithmetic unit. block, since the main time required to perform an elementary FFT operation is spent on writing and reading operands when accessing the memory block. In addition, in a number of spectral corrective tasks translational signal processing is necessary to simultaneously compute Fourier transform three or even four sequences of real numbers, which can not provide the known device. The purpose of the invention is to increase the speed of delivery and to expand the functionality of the device, which consists in calculating the conversion of up to four sequences of input samples simultaneously. The goal is achieved by the fact that the device for realizing a non-redundant fast Fourier transform algorithm containing an arithmetic unit, a permanent memory unit, a first RAM unit and a control unit, the output of the first RAM unit and the output of the fixed memory unit are connected respectively, to the input of the operands and the input of the coefficients of the arithmetic unit, the output of which is connected to the information input of the first random access memory unit, the first and second outputs of the control unit are connected to the ad the primary inputs of the first memory block and the constant memory block, respectively, the third output of the control unit is connected to the write / read control input of the first RAM block, the fourth output of the control unit is connected to the sync input of the arithmetic unit, contains the second memory block , the fifth and sixth outputs of the control unit are connected respectively to the address input and the control input of the write-connect of the second memory block, the seventh and eighth outputs of the block Regents podklmcheny to inputs of first and second handling units RAM memory, respectively, the second output of the block random access memory connected to the input operands of the arithmetic unit, wherein the control unit comprises a synchronization unit, two triggers, n-bit counter (n logjN; N is the sample size), (n + 1) the bit register of iterations, the node of the elements And, the node of the formation of the inverse code, the element And, two subtractors, two (n + O-bit of the ring shift register and the node of the lock, the first output of the node synchronization is connected to the counting input of the first trigger, the output of which is connected to the counting input of the second trigger, the first input of the And element and to the information inputs of the first bits of the first and second circular shift registers, the forward output of the second trigger is connected to the counter input, which subtracts the input of the first subtraction and the first input of the blocking node, the inverse output of the second trigger is connected to the subtractive input of the second subtractor and to the second input of the blocking node, the parallel output of the counter is connected to the first information input of the node of the inverse code and to the third input of the blocking node , the counter overflow output is connected to the control input of the shift register of the iterations, the parallel output of the register of iterations is connected to the second information input of the node of the elements And, the output of the first The code of the iteration register is connected to the control input of the AND node, to the second input of the Inc. element to the fourth input of the blocking node, the output of the (n + 1) -th bit of the register of iterations is connected to the fifth input of the blocking node, the output of the inverse code generating node connected to the summing inputs of the first and second subtractors, the outputs of which are bit-wise connected to the information inputs of the bits from the second to (n + 1) -th first and second ring shift registers, respectively, the shift control inputs of the first and second ring registers move in! respectively connected to first and second outputs of the lock assembly, the outputs of the second ring shift register unit elements, and a direct output of the second flip-flop, the second output of the synchronization unit, the output of the first ring shift register negated output of the second flip-flop, a third and fourth outputs of the lock assembly; are the outputs of the control unit from the first to the eighth, respectively. In addition, the blocking node contains elements, SHS, NOT, three modulo-two adders, two H-NOT elements, six AND elements and a trigger, with the element input NOT being the fourth input of the blocking node and connected to the first inputs of the first adder module two and element iijttl, the second input of the first modulo-two adder is the fifth input of the blocking node, inputs of the ISh1E element from the first to the fifth are the corresponding bits of the third input of the blocking node, and the nth input of the 1ShI element is NOT connected to the inverse trigger input, output e The unit is NOT connected to the first inputs of the first and second elements H-NOT, as well as the first and second elements I, the output of the element ISH1-NOT connected to the second input of the element OR, the output of which is connected to the first inputs of the third and fourth elements P, the second inputs of the third and the fourth element H are respectively the first and second inputs of the blocking node, the output of the third element AND is connected to the second input of the first element H and to the direct output of the fifth element And, the output of the fourth element And is connected to the second input of the second element H and To the direct input of the sixth element H, the inverted inputs of the fifth and sixth elements H are connected to the output of the first modulo two outputs of the fifth and sixth elements I are the third and fourth outputs of the blocking node, the direct and inverse outputs of the trigger are connected to the second inputs of the first and second elements AND-NOT, respectively, the outputs of the first and second elements H-NOT are connected to the first inputs of the second and third modulo-two adders, the second inputs of which are connected to the outputs of the second and first elements AND Naturally, the outputs of the second and third modulo adders are second, respectively, and the first outputs of the blocking node. FIG. 1 shows a functional diagram of the device for implementing the non-redundant fast Fourier transform algorithm; Fig. 2 is a functional diagram of the control unit; in fig. 3 - blocking node is functional. The device contains arithmetic unit 1, block 2 of permanent memory, blocks 3 and 4 of RAM, block 5 of control, including a node of elements AND 6, register 7 iterations, counter 8, triggers 9 and 10, node 11 synchronization node 12 forming an inverse code, the element And 13, node, 14 block, subtractors 15 and 16 and the ring 17 and 18 shift registers. The blocking node contains the elements AND-NOT 19, the elements AND 20-22, the adders 23 modulo two, the element; .. NOT 24, the adder 25 modulo two, the element USH 26, the trigger 27 and the element ILN-NOT 28. The device for implementing The redundant FFT algorithm works as follows. The four valid input sample sequences are represented as two complex, with one complex sequence located in the first RAM block 3 in binary-inverse order, and the other in the second block 4 OD in direct order. Control block 5 - {CU} generates address codes of operands selected from the first 3 or second 4 blocks of the OD and entered into the arithmetic block 1, designed to calculate elementary FFT operations of the form A i BW, where A and B are the values of two points involved in the conversion according to the directed FFT graph with a constant structure, and W - the values of the exponential factors stored in the block 2 of the permanent memory (Ш1) and counted by the address codes also produced by the UE 5, the first 3 and the second 4 OP blocks work in read mode- piis and post-reading, respectively. The two operands A and B are selected from the first OP block 3 and subjected to an elementary FFT transformation in the arithmetic block 1. Operands C and D are selected from the second 4 OP block and simultaneously the operands previously selected from the second 4 OP block are copied to the first OP block 3 and converted to an arithmetic unit t. Next, the transformed operands A and B are rewritten from the arithmetic unit I to the second OP unit 4, the operands C and O are converted, and from the first OP unit 3 the next pair of operands is read. The transformed operands C and D are put into the first block 3 OD, the operands from the second block 4 OD are read, and the next operands after A and B are converted into a pair of operands, etc. This processing order is retained for all subsequent selectable operands. Thus, the first 3 and second 4 OP blocks exchange information, and during the exchange, an elementary FFT transform is calculated. After the end of the next iteration, the py is rebuilt and ensures the selection of operands from the OP blocks according to the changing direction of the FFT graph. After the iterations of the FFT are completed, an additional iteration is needed when implementing a redundant algorithm. The calculated values — the spectra of real sequences at positive frequencies are successively read from the output of the arithmetic unit 1, with first the spectra of the sequences represented as the real part, and then the spectra of the sequences represented as the imaginary part of the complex input data. The control unit 5 of the device operates as follows. Before starting the calculations, the register of 7 iterations, the counter 8 and the triggers 9 and 10 are set to the zero state. The outputs of the trigger 9 are the outputs of the control unit and determine the mode of operation of the first 3 and second 4 OP blocks (O - read, 1 write. At the control input of the node 12 of the inverse code generation set, the potential O and the signal 68 from the outputs of bits the counter 8 is fed to the summing inputs of the subtractors 15 and 16 without inverting, on the subtracting inputs of which the signals from the outputs of the trigger 9 define the modes Rewriting the code in the register and Rewriting the code in the register with the subtraction of the unit, respectively. the second outputs of block 14 determine the operation modes of registers 17 and 18. Overwriting the code directly or Overwriting the code with an annular shift to the right by one bit, respectively.On the third and fourth outputs of the blocking block, signals of access to the OP (high potential) and resolution are formed Circulation (low potential). The interdiction is performed when the first and sixth outputs of the control unit 5 appear in the address codes by which the first two operands in the first iteration of the FFT are written to the OP blocks. For all other iterations of the FFT, a deny signal is not generated. In addition, when performing additional iteration of repacking, it is prohibited to write information into the cells of the OP blocks. Upon receipt of the clock pulses at the input of the trigger 10, its state, as well as the state of the trigger 9, the counter 8 and the register of iterations 7, changes. The signals from the outputs of the bits of the counter 8 through the node 12 in the forward or inverse code are fed to the inputs of the subtractors 15 and 16, where the unit is subtracted from the lower bit of the write address code of the second, unit 4 OP, and then the first unit 3 OP, respectively. The address codes from the outputs of the bits of the subtractors 15 and 16 also receive the information inputs of the first 17 and second 18 shift registers. In addition, the inputs of the first bits of registers 17 and 18 receive signals from the output of flip-flop 10, the state of which, depending on the potentials at the first and second outputs of block 4, is recorded either at the first register bit (at control input O) , or the last bit of the register when all information is shifted towards the lower bits by one bit (at control input 1). When the first iteration of the FFT is performed at the third and fourth outputs of block 14, prohibitory signals appear. Accessing the OD blocks during the generation of the write codes for the first pairs of operands4 In subsequent FFT operations, the access prohibition signal is not generated. The address and write address codes for the operands for the first 3 and second 4 OD blocks are shown in Table 1. After the end of the iterations of the FFT, at the output of the first bit of register 7, signal I appears. At the same time, a high potential is formed at the control inputs of registers 17 and 18, and at the third and fourth outputs of the node 14 the signals for writing to OP blocks . In this mode, the repacking of information stored in the OP blocks is performed. Address codes readable opera. The DOVs are listed in Table 2 / here, as in Table I., the address codes correspond to the eight point directed FFT graph. The formation of address codes to the block 2 of the permanent memory (n is carried out by a group of nodes: node of elements 6, counter 8 and register 06110 11 of the messages 7, which operates in the mode of entering 1 into the highest bit when all information is shifted towards the lower bits The shift and entry of information is carried out by the signal of the state transition of the high-order counter of 8 out of 1 into O. funkts ionic possibilities when increasing the speed and high efficiency of using the arithmetic unit of the device. In this case, the efficiency of using the arithmetic unit is maximum.

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Claims (1)

1. DEVICE FOR IMPLEMENTING A REDUCTIVE LURIER FAST TRANSFORMATION ALGORITHM containing an arithmetic block, a read-only memory block, a first random access memory block and a control unit, the output of the first random access memory block and the output of the constant memory block being connected respectively to the input of the operands and the input of the arithmetic coefficient block the output of which is connected to the information input of the first RAM block, the first and second outputs of the control unit are connected to the address inputs of the first RAM block memory and read-only memory, respectively, the third output of the control unit is connected to the recording control input by reading the first RAM unit, the fourth output of the control unit is connected to the synchronizing input of the arithmetic unit, characterized in that, in order to improve performance and expand the functionality of the device, consisting of computing the transformation simultaneously up to four sequences of input samples, it contains a second block of RAM, with the fifth and sixth output The control unit is connected respectively to the address input and the write-read control input of the second RAM block, the seventh and eighth outputs of the control block are connected to the access inputs of the first and second RAM blocks, respectively, the output of the second RAM block is connected to the operand input of the arithmetic block, the control unit contains a synchronization node, two triggers, a n-bit counter (n = log ₂ N; N is the sample size), (n + 1) -bit register of iterations, node of AND elements, node of inverse code generation, element AND ^, two subtractors, two (n + 1) -bit ring shift register and block node, and the first output the synchronization node is connected to the counting input of the first trigger, the output of which is connected to the counting input of the second trigger, the first input of the Peak element to the information inputs of the first bits of the first and second ring shift registers, the direct output of the second trigger is connected to the counter input, subtracting the input of the first subtractor I and to the first input of the lock node, the inverse output of the second trigger is connected to the subtracting input of the second subtractor and to the second input of the lock node, the parallel output of the counter is connected to the first information input of the element node AND, to the information input of the node for generating the inverse code and SP is to the third input of the lock node, the counter overflow output is connected to the iteration register shift control input, the parallel iteration register output is connected to the second information input of the AND element node, the output of the first bit of the iteration register is connected to the control input of the AND element node, to the second the input of the Peak element to the fourth input of the blocking node, the output (n + 1) ~ th, the discharge of the iteration register is connected ~ to the fifth input of the blocking node, the output of the inverse co-forming node is connected to the summing inputs of the first о and the second subtractor, the outputs of which are bitwise connected to the information inputs of the bits from the second> second (first + 1) th first and second ring shift registers, respectively, the shift control inputs of the first and second ring shift registers are connected respectively to the first and second outputs of the node blocking, outputs of the second annular shift register, AND element node, direct output of the second trigger, second output of the synchronization node, output of the first circular shift register, inverse output of the second trigger, third and fourth the outputs of the interlock node are the outputs of the control unit from the first to the eighth, respectively, MH. The device according to claim 1, with πη4 said that the blocking unit contains the elements OR-NOT, OR, NOT, three adders modulo two two AND-NOT elements, six AND elements and a trigger, and the element input It is NOT the fourth input of the blocking node and is connected to the first inputs of the first adder modulo two · and the OR element, the second input of the first adder modulo two is the fifth input of the blocking node, the inputs of the OR-HE element from the first to the ηth are corresponding bits of the third input of the blocking unit. ki, where the ηth input of the OR element is NOT connected to the inverse input of the trigger, the output of the element is NOT connected to the first inputs of the first and second elements of NAND, as well as the first and second elements of AND, the output of the element OR is NOT connected to the second input of the element OR, the output of which is connected to the first inputs of the third and fourth elements AND, the second inputs of the third and fourth elements AND are respectively the first and second inputs of the blocking node, the output of the third element And is connected to the second input of the first '• element And and to the direct output 'go el element And, the output of the fourth element And is connected to the second input of the second element Inc to the direct input of the sixth element And, the inverse inputs of the fifth and sixth elements And are connected to the output of the first adder modulo two, the outputs of the fifth and sixth elements And are respectively the third and fourth outputs of the node blocking, direct and inverse outputs of the trigger are connected to the second inputs of the first and second elements AND NOT, respectively, the outputs of the first and second elements AND are NOT connected to the first inputs of the second and third adders modulo d VA, the second inputs of which are connected to the outputs of the second and first elements AND, respectively, the outputs of the second and third adders modulo two are respectively the second and first outputs of the blocking unit.