SU1298766A1 - Device for generating addresses of fast fourier transform processor - Google Patents

Abstract

The invention relates to computing and can be used in the construction of specialized processors that implement the fast algorithm, the transformation from 00 to O5

Description

Fourier for addressing operands in digital signal processing. The purpose of the invention is to increase the speed of the device. The goal is achieved due to the fact that the device for

The invention relates to computing and can be used to construct specialized processors that implement the Fast Fourier Transform (FFT) algorithm for addressing operands in digital signal processing.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a functional diagram of synchronizer j in FIG. 3; timing diagrams: synchronizer operation; in fig. 4 - blocking node is functional

The device for generating addresses of the fast Fourier transform processor consists of synchronizer 1, counter 2, shift register 3, R locking nodes (bit) 4.1-4.R and registers 5-9.

Synchronizer 1 (Fig. 2) contains a 1K-trigger 10, shift register 11, elements AND 12-14, element OR 15 elements AND 16 - 26, element OR 27, element 28 and element OR 29, element OR 30.

Destination 4 blocking contains the element AND-NOT 31, the element OR-ME 32 and two adders 33 and 34 modulo two.

The device for generating the addresses of the fast Fourier transform processor functions as follows.

In the initial state, the counter 2 is set to the zero state in the shift register 3 and the lower first bit is set to one, and the remaining R bits are set to the zero state, the shift register 11 of the control unit 1 is set to at which at its output A1 - a logical unit, and at outputs A2 - A4 - a logical zero, 1K-trigger 10 is reset, i.e. on the inverse output of his logs

The address of the fast Fourier transform processor consists of synchronizer 1, counter 2, shift register 3, interlocking nodes A.1-A.R, and registers 5-9. And il.

About 5

0

5 0 s

five

is a logical unit, and at the direct output - a logical zero. The control input of register 11, which is included as a ring register, receives clock pulses and a logical unit, appears sequentially at the outputs A1, A2, A3, A4, again at A1, etc. The control signals are produced by a circuit consisting of elements 10, 12-30 (Fig. 2), shown in the timing diagram (Fig. 3), where TI is the clock pulses, A1 - A4 are the outputs of the register 11, input 2 is the signal to synchronizer input 1, out. 1, out 2 ... 14 - signals, respectively, on the first, second, ..., fourteenth outputs of the synchronizer 1, TG. U - a signal on the direct output of the 1K-flip-flop 10.

Consider the operation of the device when operating in the i-th cycle of the i-ro stage of the fast Fourier transform algorithm. During the n-th cycle, an n-pair of operands should be addressed to read them from the random access memory and (n-1) - a pair of operands for writing the result of processing the operands of the preceding cycle into a random access memory. To output the addresses of the operands of the previous cycle, the first, second, third, and fourth registers of the address of the operand are used. The bit outputs of these registers are interconnected as well as with the bit outputs of the first register 5 and are the device outputs from which the address of the operand is read. The outputs of these registers have three steady states. At any time, only one of these registers is active, namely, the one to which the read signal from synchronizer 1 is fed, and the outputs of the other registers

are at this moment in time in a high impedance state. Recording and reading of information in registers 6-9, and Takme in register 5 are made in accordance with the timing diagram shown in FIG. 3. The four registers of the address of the operand are divided into two groups. Registers 6 and 7 belong to the first group, registers 8 and 9 belong to the second group. In the first and second cycles of the nth cycle of the fast Fourier transform algorithm, the addresses of the pair of operands of the nth cycle are written into registers related to one group, then IK-tpHrrepa 40 of synchronizer 1 is switched, which selects the other group of registers, and in the third and fourth cycles of the nth cycle, the addresses of the pair of operands are read. (n-l) -ro cycles from this group of registers for writing the result of processing this pair of operands into random access memory. In the next

thirty

35

40

The first (n + 1) th cycle of the fast 25 register algorithm 6. In the second half of the Fourier transform, in the first two cycles, the addresses of the operands are written in the same registers of the second group, from which addresses were read in the nth cycle and only at the end the second clock cycle; the flip-flop 10 of synchronizer 1 switches over to the operation of the first group of registers. The addresses of the pair of operands of the fast Fourier transform algorithm at each stage are distinguished by information in one bit, the number of which corresponds to the stage number of the fast Fourier transform algorithm, and the address of the first operand of the nth pair of operands contains a logical zero in this bit, and the address of the second operand is logical unit. Therefore, this bit of counter 2 is blocked and replaced by either a logical zero or a logical unit in accordance with the control signals received at the blocking nodes 4 from synchronizer 1 and from shift register 3. The stage number of the fast Fourier transform algorithm corresponds to the state of the shift register 3, in accordance with this state, at its outputs 1, 2, 3 ,, .., i-1, i + 1R + 1

there is a logical zero level, and output 1 is a logical one level. These levels arrive at the fourth inputs of the locking nodes A, with information from the output 45

55

first tact signal from the nth output. synchronizer 1 reads the address of the first operand of the nth pair of operands from register 5; in the first half of the second clock, the second operand of the nth pair of operands is written to the register 5 from the sixth output of synchronizer 1 and the signal from the eighth output of synchronizer 1 to the register 7 (with the signal at the third output of the synchronizer 1 set to the logical zero state). In the second half of the second cycle, the address of the second operand of the nth pair of operands from register 5 is read from the fifth output of synchronizer 1, as well as the signal from the first output of synchronizer 1, overwriting the address of the second operand of the nth pair of operands of the first transformation in counter 2 Fourier. At the end of the second clock cycle, the 1K-flip-flop 10 of the synchronizer 1 changes its state to the opposite, which switches to the CYCLE of operation of the second group of registers if the first group of registers was working or switching to a cycle the work of the first group of registers, if the second group worked. In the first half of the third clock cycle, the address of the Second operand of the nth pair of operands from register a 5 is continued. In the second half of the third clock cycle, and

fO

jr -

2

four

21-2

20

gtoi / 7-2 7 dov, z ,, .., /,, ..., /.

the counter 2 enters the inputs of the locking nodes 4 and passes to the output of the locking nodes 4 without changing (for the data of the outputs of the counter 2, the corresponding locking nodes are enabled according to the repeater scheme), and the information from the th output of the counter 2 is blocked and replaced with information coming from the output synchronizer 1 to the input of the corresponding blocking node (blocking node of the 2nd discharge of the counter is switched on according to the third input of the inverter). In the first half of the first clock cycle, the signal from the corresponding output of synchronizer 1 records the address of the first operand of the nth pair of operands in register 5 (the third output of synchronizer 1 is set to the state of the logical one), and also the signal from the seventh output of synchronizer 1 — the address of the first operand nth pair of operands

0

five

0

5 register 6. In the second half

five

five

first tact signal from the nth output. synchronizer 1 reads the address of the first operand of the nth pair of operands from register 5; in the first half of the second clock, the second operand of the nth pair of operands is written to the register 5 from the sixth output of synchronizer 1 and the signal from the eighth output of synchronizer 1 to the register 7 (with the signal at the third output of the synchronizer 1 set to the logical zero state). In the second half of the second cycle, the address of the second operand of the nth pair of operands from register 5 is read from the fifth output of synchronizer 1, as well as the signal from the first output of synchronizer 1, overwriting the address of the second operand of the nth pair of operands of the first transformation in counter 2 Fourier. At the end of the second clock cycle, the 1K-flip-flop 10 of the synchronizer 1 changes its state to the opposite, which switches to the CYCLE of operation of the second group of registers if the first group of registers was working or switching to a cycle the work of the first group of registers, if the second group worked. In the first half of the third clock cycle, the address of the Second operand of the nth pair of operands from register a 5 is continued. In the second half of the third clock cycle, and

; In the first half of the fourth, the signal from the thirteenth output of synchronizer 1 reads the register 8, which stores the address of the first operand (n-1) -th pair of operands. In the first half of the fourth clock cycle, the signal from the second output of the synchronizer is added to the counter 2,

the first operand of the nth pair of operands from register 5 is read into the logical unit. In the first half of the second cycle, the address of the second operand of the nth pair of operands is written from the sixth end of the synchronizer 1 to the register 5 and the signal from the eighth synchronizer output 1 in

In the second half of the fourth so-10 register 7 (with a signal on the fourth

that, as well as in the first half of the subsequent first clock cycle, the address of the second operand (p-1) -th pair of operands from register 9 is read by the signal from the fourteenth output of synchronizer 1,

The cycle repeats until all pairs of operands are processed through all stages of the fast Fourier transform algorithm, after which the device begins to generate addresses of operand pairs of the special stage of the non-redundant fast Fourier transform algorithm.

at the outputs of the shift register 3-1,2 ,,,,, 25 cycle of the first group of registers.

R sets the logical zero level, and output R + 1 sets the level of the logical unit. None of the bits of counter 2 are blocked by interlocking nodes 4. Information from the bit outputs of counter 2 passes to the output of locking nodes 4 or with inversion (the signal at the fourth output of synchronizer 1 is set to the state of logical ones), or without inversion (the signal at the fourth output of synchronizer 1 is set to logical zero) and arrives on the information inputs of registers 5-9,

Consider the operation of the device when working in the nth cycle of a special stage of the fast Fourier transform algorithm.

In the first cycle, the signal at the fourth output of synchronizer 1 inverts the bit outputs of counter 2 by locking nodes 4. In the first half of the first cycle, the address of the first operand of the nth pair of operands is recorded by a signal from the sixth output of synchronizer 1 to the register 5 and a signal from the seventh synchronizer output. 1 to register 6; In the second half of the first clock cycle, a signal from the second output of the synchronizer is used to add one to counter 2, and the signal at the fifth output of synchronizer 1 is set to a logical one Itza manufactured and reading the first operand address of the nth pair of operands from the register 5. During the first half of the second cycle is performed recording of the second operand address of the nth pair of operands signal from the sixth synchronizer vpsoda 1 in the register 5 and the output signal from the eighth synchronizer 1

the output of synchronizer 1, set to a logical unit), in the second half of the second cycle and in the first half of the third cycle with a signal

The fifth output of synchronizer 1 reads the address of the second operand of the nth pair of operands from register 5 "At the end of the second clock cycle, trigger 10 with the counting input of synchronizer 1

changes its state to the opposite, which makes switching to the cycle of the second group of registers, if the first group of registers was working, or switching to

if the second group worked. In the second half of the third cycle and in the first half of the fourth cycle, the signal from the thirteenth output of the synchronizer 30 reads the address of the first operand (n-1) -th pair of operands from register 8. In the second half of the fourth cycle and in the first half of the first cycle the next An n + 1) -th cycle, the signal from the fourteenth output of synchronizer 1 reads the address of the second operand (n-1) -th pair of operands from register 9, then the cycle repeats

40 BEFORE all pairs of operands of the non-redundant stage of the fast Fourier transform algorithm are processed, after which the device finishes its operation,

45

Claims (1)

Invention Formula A device for generating addresses of a fast Fourier transform processor containing a synchronizer, first register, R blocking nodes (R is the address width) and a counter, the output i-ro (i 1, R) of which bit is connected to the first input of the 1st 55 blocking node whose output is connected to the information input of the i-ro bit of the first register, the output of the bit bit of which is the output of the i-ro bit of the device address and sub-7 keys to the i-ro input of the counter, the counting summing inputs of which are connected respectively to the first and second outputs of the synchronizer, the third and fourth outputs of which are connected respectively to the second and third inputs of the i-ro block, the read enable input and the write enable input of the first register connected, respectively, to the fifth and sixth outputs of the synchronizer, the clock input of which is the clock input of the device, the 1st block, the blocking node contains the first and second modulo-two adders, the AND-NES element and this the OR-NOT unit whose output is connected to the first input of the first adder modulo two, the output of which is connected to the first input of the second modulo-two adder, whose output is the output of the blocking node whose first input is the first input of the element OR NOT; the second and third inputs of the blocking node are, respectively, the second input of the second modulo two adder and the first | .th input of the NAND element whose output is connected to the second input of the first totalizer 12 1298766 Modulo two, the second inputs of the OR-NOT and the NAND element are interconnected and are the fourth input of the blocking node, due to the fact that, in order to increase speed, the shift register and the second, third , fourth and fifth registers, ix information entries the bits of which are connected to the output of the i-ro blocking node, the fourth input of which is connected to the output of the i-bit digit of the shift register, the clock input of which is connected to the transfer output of the counter, the input of the 1st bit of which is connected to the outputs ix of the second bits the third, fourth and n of the registers, the write enable entries of which are connected respectively to the seventh one, The eighth, ninth and tenth outputs of the synchronizer, the eleventh, twelfth, thirteenth and fourteenth outlets of which are connected to the read enable inputs of the second, third, fourth and nth registers respectively, and the shift register shift output is connected to the synchronizer stop input. TH .AAAAAAAAAAAAAALA 32 Editor, E. Papp Thess. four Compiled by A. Baranov Tehred L. Serdyukova Order 891/52 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, st. Project, Fig.Z J4 Proofreader O.Lugov