SU503296A1 - -Shift shift register - Google Patents

Description

(54) N-DISPLAY SHIFT REGISTER

rep memory, the second is a switching trigger with four elements “And at the input. The clock pulse generator 1 has two output stages 2 and 3 / g of the digit of the register built on logic elements 4-7, (n - {+ 1) -th bit of elements 8-11. The second trigger n-bit on the elements 6-7 contains, respectively, the valves 12, 13 and 14, 15. In addition, the same trigger contains additional valves 16 and 17. The first inputs of these valves are connected to mutually inverse outputs of their own trigger. The clock inputs of bits from 1st to “-Y are connected to the output of the 2 GTI cascade, and the second inputs of additional gates 16 and 17 of the second trigger of the n-bit discharge and clock inputs of bits from (fi + l) -ro to L- nd connected to the output of the cascade 3.

The diagrams of the n-th bit operation on elements 4-7 and (n + 1) -cc bits on elements 8-I are shown in FIG. 2

At time ti, the pn-bit receives information of the type 0101 ... from the (n-1) -th bit in the forward and inverse U codes and writes it to the first trigger on elements 4 and 5. At time / 2 at the outputs of the second trigger (elements 6 and 7), the change of information (dotted line) must begin, which will correspond to the new information recorded in the bit at time ti. However, at ti, a clock input from the output of cascade 3 arrives at the clock input of the additional valves 16 and 17, which ensures that the second trigger on elements 6 and 7 remains unchanged until tz due to the additional valve 17. Therefore, the change in information on the outputs of the second trigger (solid line ) starts not from the time tz, but from the time tz, after the end of the clock pulse of the cascade 3. At the time ta / gth bit, it receives information from the (n -) - th bit and writes it to the trigger on elements 4 and 5. At the time and ts (and - (- 1) -th bit takes information from the -th bit and writes it to the first trigger on elements 8 and 9. At time 4, the second trigger on elements 6 and 7 / g of the bit should change its state according to the information obtained at ta (dotted line).

However, at the moment 1h, a clock pulse from cascade 3 arrives at the clock input of the additional trigger valve 16 on elements 6 and 7 and thus ensures the "interception of the previous state of this trigger. The trigger on elements 6 and 7 changes its state at time t (solid line) after the end of the clock pulse. The second trigger on the elements 10 and 11 (p4-1) -th bit

at time ti also changes its state in accordance with the information received at time ta.

The information in the register is processed without failures, regardless of the presence of a clock pulse shift in the clock series of cascades 2 and 3, since the second trigger of the n-bit with additional gates 16 and 17 has a structure that provides for "interception of its previous state from beginnings

the first (second) to the end of the second (first) clock pulses.

The performance of the proposed shift register is increased, since the transfer of information between the bits is not disturbed and does not have additional delays (which is a consequence of the simplification of the register) when it is clocked from both two output stages and three or more GTI output stages.

Claims (1)

Invention Formula N-bit shift register containing in each bit two RS flip-flops with four elements “And at the input, the outputs of the first trigger are connected to the corresponding inputs of the second trigger, the clock inputs (1-n) of the register bits are connected to the output of the first output stage of the clock generator, the clock inputs (n-yV) of the register bits are connected to the output Its second output stage, characterized in that, in order to replenish and increase the speed of the register, in it The second trigger of the n-th register bit contains additional elements “And at the input, the first inputs of which are connected to the inverse output of the trigger, and the second to the output of the second stage of the clock generator. 2 different in --- GTPIGG1-. MP fiJ, b g. -T j-U L rLj A, r- | - I nJji wl | -C PgP-u1. 1 MlJ :: i: t ::: DJ {n 1 -pazff ff N-bit d 810 ъ.