SU1506553A1 - Frequency to code converter - Google Patents

Abstract

The invention relates to computing and can be used in the composition of frequency-pulse computing devices for information-measuring systems operating with frequency sensors. The invention allows to increase the speed of the device due to the fact that the device containing the reference frequency generator 11, the divider block 12, exponential generators 8 and 9, the keys 4-6, the key block 13, the counter 7, the comparator 10, the delay elements 2.3 The shaper 1, the re-scaling unit 15, the scaling unit 14 and the register 16 are introduced. The introduction of these blocks reduces the conversion time, which in turn allows the input signal frequency range to be expanded. 1 hp f-ly, 3 ill.

Description

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The invention relates to computing and can be used as an input information converter, specified by a low or infra-low frequency pulse stream, and also as part of a frequency-pulse computing device for information-measuring systems operating with frequency sensors.

The purpose of the invention is to increase the speed and, consequently, increase the operating range and reduce the dynamic error.

FIG. 1 shows a block diagram of a converter; FIG. 2 is a timing diagram illustrating the operation of converter i in FIG. 3 is a scale block diagram.

The device contains a driver 1, two elements 2 and 3 delays, three keys 4-6, a counter 7, two exponential generators 8 and 9, a digital comparator 10, a reference frequency generator 11 (MFR), a divider block 12, a key block 13, a block 14 scaling, re-scaling unit 15 and register 16, output bus 17, input bus 18.

Scaling unit 14 is provided on memory element 19 and comparator 20.

The device works as follows.

The value of Np, proportional to the frequency F of the input pulse sequence, is obtained in two cycles. In the first cycle, the value of Ny is determined, which is proportional to the period T of the frequency of the input signal, by counting the pulses of the calibrated frequency that fill the period between two adjacent input pulses. As NT is formed, its code passes through a series of consecutive values of N. (Fig. 2). In accordance with the known expression Np M const for each value N. The value Np is chosen. . The last pair of the NT |, NTH values (in Fig. 2 —N-J N, NF, N.) is the initial steps for the second conversion. In the second cycle, the hyperbolic transformation of the magnitude of NT to the desired value Np occurs by simultaneous exponential interpolation of the N – j–

0

0 5

five

the value of N and the value of Nj to the desired NP (time point t). The time t shows the conversion period of the known device.

Consider the operation of the circuit device (Fig. 1).

The input pulses are fed to the input 18 of the imaging unit 1 pulses. The signal from the imager to register 16 from the scaling block receives the value code N -, -, exponential generator 8 receives the value code N.J. from counter 7, and to exponential generator 9, the code of the value of Np from the re-scaling unit 15. The signal from the output of delay element 2 zeroes the counter 7, sets the initial values of N and NF in the scaling and rescaling units, and the value of N-j in the second group of outputs of memory element 19. and opens the keys 5 and 6 for passing from the outputs of the block 12 dividers of the corresponding clock pulses to the inputs of the exponential generators 8 and 9, in which the exponential interpolation begins. A pulse from the output of the delay element 3 opens the key 4 and the calibrated frequency pulses begin to come to the input of the counter 7. Exponential interpolation occurs until the code value at the output of the exponential generator 8 matches the code value at the output of register 16. At the time of comparison, the comparator 10 absorbs a signal that closes the keys 5 and 6, thereby stopping the operation of the exponential generators, and through the block 13 of keys transfers the contents at the output of the exponential generator 9 to the output of the device.

When the code in the counter 7 reaches the value N (N- and-etc.), the comparator 20 generates a signal to set the output of the scaling block 14 to the code value NT- (N, etc.), according to the second group of outputs of the memory element 19 - values of the N code (N, etc.), and at the output of the re-scaling unit - values of the Np code (Np, etc.).

The choice of the values of N. (N p-) depends on the size of the working range and the required speed. FIG. 2 shows the following selection scheme.

these values :. NT-N, N ... N

-th m t m, - - / Ng, ..., Ny .i Ng. Relevant

values for Np; are as follows:

NF, Nt

2 N

F max t

lax and

Np ,,,.: .-, N .. 2- N, In general, the value of N

 four

Np, may not be a multiple of a number, then the rescaling unit is a memory unit. With

multiples of N

g;

and N p. blocks 1

one

Claims (2)

1. The frequency-code converter containing a serially connected driver, the first and second delay elements, the first key and the counter, whose input is combined with the first inputs of the second and third keys, respectively, and connected to the output of the first delay element, the second inputs of the second and third keys are combined with control input of the key unit and connected to the output of the comparator, the first group of inputs of which is connected to the corresponding outputs of the first exponential generator, the first input of which is connected to the output the second key and the second input are combined with the first input of the second exponential generator and connected to the output of the imaging unit, the outputs of the second exponential generator are connected to the corresponding information inputs of the key block whose outputs are the output width of the device, the second input of the second exponential generator is connected to the output of the third key, the output of the reference frequency generator is connected to the input of the divider unit, the first, second and third outputs of which are connected to with , 9 , ten 15 20 the second input of the first key and the third inputs of the second and third keys, respectively, n outputs of the counter are connected to the input group of the first exponential generator, respectively, where n is the counter size, the driver input is the input bus of the device, characterized in that, in order to increase speed, a register, a scaling unit and a re-scaling unit are introduced, the outputs of which are connected to the input group of the second exponential generator, respectively, the first input is connected to the output of the scaling unit The second input is combined with the first input of the scaling unit and connected to the output of the first delay element, 1 of the n outputs of the counter, where 1 4 n are connected to the input group of the scaling unit, respectively, the output group of which is connected to the corresponding information inputs of the register, whose outputs connected to the corresponding inputs of the second group of inputs of the comparator, and the control input is connected to the output of the imager. 2. The converter according to claim 1, characterized in that the scaling unit is made on a memory element and a comparator, the first group of inputs of which is 35 is a block input group, and the output is connected to the first input of the memory element and is the output of the block, the second input of the memory element is the first input of the block, the first group of outputs of the memory element is the output group of the block, the second group of outputs is connected to the second group comparator inputs. thirty 40 O tot i t