SU465748A1 - Phasing method when transmitting information by cyclic code - Google Patents

Description

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The invention relates to the field of measurement technology and can be used when transmitting information encoded with a cyclic code through discrete communication channels.

A known method of phasing when transmitting information using a cyclic code consists in checking the segments of the received information sequence for its correspondence to the producing polypome, and receiving a discrepancy signal, which is used to determine the shift of the received information sequence before entering the phase matching phase.

A disadvantage of the known method is that it takes a long time to enter into phase matching due to the fact that the information sequence shifts sequentially — one character for each check, which leads to an increase in the number of checks required for synchronization.

In order to increase the rate of occurrence in synchronism when using a mismatch signal to determine the amount of shift of the received information sequence, a pulse signal is formed, the duration of which is equal to the maximum possible number of shift symbols, and using the generated pulse signal, the necessary number of

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clock pulses. The operation of forming a pulse signal, the duration of which is equal to the maximum possible number of shift symbols "m of the received information sequence with the number of symbols" n in the code combination, the number of check symbols of the code "g and the high bit number" i in the shift signal recording, is performed in accordance with with identities; t .- / g - /, 2, 3 ... g

, at /: -. 1.

The drawing shows the block diagram of the device that implements the proposed method.

The device contains a shift register 1, which includes adders 2 and 3, trigger cells 4-7, a clock counter 8, a inhibitor circuit 9, a phasing inhibitor trigger 10, a reset driver 11, a decoder 12, an OR circuit 13, drivers 14 -18 pulse duration; matching schemes 19-22.

The inputs of the decoder 12 are connected to the outputs of shift register 1, and the outputs of the decoder determining the number of shift characters are connected to the OR circuit and to the formers, the output of the OR circuit is connected to the input of the phasing inhibit trigger, the outputs of the formers are connected to the first inputs

coincidence circuits, on the second inputs of which, via the driver, the output of the fazirovapi prohibition trigger is connected, the outputs of the coincidence circuits are connected to the circuit inputs.

The device works as follows.

The information signal sequence enters the shift register and is processed in it in the same way as in the known device.

After writing to the shift register of the last digit to be divided, the final remainder is fixed in it or, if the combination is in the allowed code sequence, the register goes to the zero state; The nth pulse of the first clock frequency passes signals from the first triggers of the register cells through the decoder valves.

If the trigger cells of the register after recording the last digit of the dividend are in the zero state, there is no signal at the output of the decoder; the recording of pulses into the counter and information signals into the shift register occurs without change.

If, when writing to the register of the last digit to be divided, not all the triggers in the register are set to the zero state, then the signal, depending on the state of the trigger cells, will be on one of the decoder inputs, determined by their number of shift symbols.

This signal from the output of the decoder through the OR element is applied to the prohibition trigger, translating it into a single state.

At the same time, the signal from the output of the decoder enters the driver, producing a signal of the desired duration.

The inhibitor trigger 10 is transferred by the / gth pulse of the second clock frequency to the zero state, and this pulse sends a signal to the driver 14.

The duration of the signal from the driver 11 is the same as the duration of the longest signal issued by one of the drivers.

Thus, the signal of the desired length passes through the appropriate coincidence circuit to the input of the inhibiting circuit, the prohibition of the required number of pulses from the GTI, i.e., the shift of the information sequence of signals by a certain number of symbols.

If at the next check the remainder is not zero, then the information sequence of signals is shifted again by the number of characters determined by the remainder and so on until the signal at the output of the decoder is missing, i.e., until the synchronous state is fixed. Thus, the proposed method allows to reduce the time of entry into synchronism.

Subject invention

Claims (2)

1. A phasing method for transmitting information using a cyclic code, which consists in checking the segments of the received information sequence for its corresponding polynomial, and receiving a mismatch signal, which is used to determine the shift of the received information sequence before entering the phasing synchronization process, characterized in that in order to increase the rate of occurrence in synchronism, when using a mismatch signal to determine the magnitude of the shift of the received information sequence They form a pulse signal, the duration of which is equal to the maximum possible number of shift symbols, and using the generated pulse signal, the necessary number of clock pulses are suppressed. 2. A method according to claim 1, characterized in that the operation of forming a pulse signal whose duration is equal to the maximum possible number of shift symbols of the received information sequence with the number of characters n in the combination of a code, the number of check characters of the code r and the number of the most significant bit i in the recording of the shift signal is carried out in accordance with the following identities: t: n - g-f 1 at /; 2, 3 ... r t - n - r with i: - 1.