SU501491A2 - Device for determining the reliability of information transmitted by a cyclic code - Google Patents

Description

one

The invention relates to telecommunications and can be used to monitor the functioning of data transmission systems.

According to the main author. St. A device for determining the reliability of information transmitted by code is known to ° 316204.

However, in the known device, due to the fact that cyclically shifting the elements of an allowed combination one element to the left also forms an allowed combination, cyclic phasing fails, infinitely long phasing, as well as erroneous phasing if there are repeated combinations in the channel, which ultimately reduces the reliability of the device.

The purpose of the invention is to increase the reliability of the device by reducing the number of false phasing failures.

For this purpose, an inversion node and a control combination control unit are entered into the proposed device, where the information signal is fed to the corresponding inputs of the shift register via the inversion node, the outputs of which are directly and through the delay element are connected to the enable and disable inputs of the inversion, respectively. the output of the inversion node is connected to the corresponding input of the phasing trigger through the control combinations control unit, to

the other inputs of which are connected to the outputs of the trigger of the error-counting circuit and the coincidence circuit, in addition, the clock pulses are fed to the corresponding inputs of the control combinations of service combinations directly and through the corresponding delay element.

The drawing shows a functional diagram of the proposed device.

The device for determining the reliability of information transmitted by the cyclic code contains a shift register 1 consisting of adders 2, 3 and triggers 4-7, a clock selection counter 8, a coincidence circuit 9, a delay element 10, a trigger 11 for the error counting circuit 12, counter 13 of affected combinations, phasing trigger 14, coincidence circuit 15, trigger 16, delay element 17, prohibition circuit 18,

counter 19 unaffected combinations; reset resetr 20, delay element 21, driver 22, inversion node 23 consisting of matching circuits 24, 25, 26, trigger 27, inverters 28, 29, 30, and service combination control block 31 from the coincidence circuits 32, 33, 34 and trigger 35, the information signal (inf.) is fed to inputs 36, Zba shift register 1 via inversion node 23 (input 37, outputs 38, 39), to inputs 40, 41 of permission and prohibition inversion

the outputs of the clock selection counter 8 are connected directly and through the delay element 10, and the direct output 38 of the inversion node 23 is connected to the corresponding input of the phasing trigger 14 via block 31 (input 42, output 43), to inputs 44, 45 of which are connected respectively to the outputs trigger 11 and match patterns 12; clock pulses (TI) are applied to the inputs 46, 47 of the block 31 directly and through the delay element 17, the input 48 is connected to the output of the counter 19, and the output 49 of the block 31 is connected to one of the inputs of the trigger 11.

The device works as follows.

In the inversion node 23, the p-bit and bit are inverted, and thus the combination of the cyclic code is restored for subsequent division into a forming polynomial.

The matching circuits 25 and 26 from the input 37 of the inversion node 23 receive information from the discrete channel to the forward (positive), and through the inverter 28 in the inverse (negative) codes. A trigger 27 gives permission for a matching circuit 25 to invert the nth bit. The coincidence circuit 26 selects a (" -1) -th clock pulse. Resolution is removed by delay element 10.

Thus, the recovered information is obtained in a cyclic code, and after the inverter 29 - negative, and after the inverter 30 - positive.

Control 31 of the combination of combinations during phasing checks the beginning of the phased combination. A necessary condition for terminating (correct) phasing in this implementation is the presence of "1 (indirect indication of service) in the first discharge of one of the correctly accepted combinations. Otherwise, the phasing of the instrument continues.

This is done as follows.

When phasing by a coincidence circuit 32, the first bit of information is checked, and in the presence of "1 flip-flop 35 is transferred to" one state, while if the counter 19 of unaffected combinations counted a specified number of correctly received combinations, a signal is generated at the output of the coincidence circuit 34 "Reset trigger 14. Otherwise, if trigger 35 is in the" zero state, after a predetermined number of correctly received combinations, a signal appears at the output of the matching circuit 33, which places trigger 11 in the "zero state." A “Error,

and phasing continues.

Claims (1)

Invention Formula The device for determining the reliability information transmitted cyclical code for auth. St. No. 316204, characterized in that, in order to increase the reliability of the operation of the device, in order to reduce the number of false faults in the phasing, the inversion node and the control combinations control unit, the information signal being fed to the corresponding inputs of the shift register through the inversion node, the inversion enable and inhibit inputs of which are connected respectively to the outputs of the clock selection counter directly and through the delay element, and the forward output of the inversion node is connected to the corresponding the entrance of the phasing trigger through the control unit service combinations, to the other inputs of which the outputs of the trigger of the error-counting circuit and the coincidence circuit are connected, in addition, the clock pulses are fed to the corresponding inputs of the service control unit combinations directly and through the corresponding delay element.