SU1247876A1 - Signature analyzer - Google Patents

Abstract

The invention relates to computing and can be used in test and functional diagnostics systems, digital devices. A distinctive feature of the proposed signature analyzer is the possibility of self-monitoring directly in the process of its operation. This is ensured by the choice of the generating denomination of the signature signature former of a certain type, namely, the type f (x) (x + 1) F (x). At the same time, such values have the property of preserving the parity of the signature when the signal of the logical zero is applied to the input of the driver and the parity changes when the signal of the logical one is applied. The additional elements entered into the analyzer allow you to quickly identify all analyzer faults that violate this property. 3 il. i (П ГС 4 00 о

Description

one

The invention relates to computing and can be used in test and functional diagnostics systems for digital devices.

The aim of the invention is to increase reliability by providing self-monitoring.

FIG. 1 shows a functional diagram of the signature analyzer; in fig. 2 shows an example of building a signature generator with the generator polynomial 9 (x) (x + .1) (); in fig. 3 - timing charts of the analyzer.

The signature analyzer contains informational 1 and synchronizing

2 inputs, shaper 3 signatures, modulo two convolution block 4, delay block 5, first and second triggers 6 and 7, modulo two adder 8, And 9 element output 10 error signal.

Block 5 delay contains the first second and third delay elements 11, 12 and 13.

The signature generator contains bit elements 14, -1, memory (for example, D-flip-flops) and elements 15 EXCLUSIVE OR.

Signature analyzer works in a consistent manner.

Before starting, all successive elements are set to the zero state (installation chains are conventionally not shown). A polynomial of the form P (x) () F (x) was chosen as the forming polynomial of the former of 3 signatures. The polynomials of this type have the following property: in the presence of a logical zero signal at the information input 1 of the driver

3, signatures in a certain cycle of its operation convolution modulo two signals from the outputs of all bits of the register of the imaging unit 3 has a constant value O or 1 depending on the previous state of the register, i.e. the signal from the output of block 4 of convolution modulo two remains unchanged when applying successive clock pulses to input 2, if information signal 1 has a logic zero signal. Otherwise, if the signal of a logical unit is applied to information input 1, the signal at the output of block 4 will change its value at each clock cycle of the synchronizing signal at input 2.

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FIG. 2 shows an example illustrating the process of forming signatures with a forming polynomial (x) x + x - -x + 1 and applying a logical zero signal to the information input. With this it is seen that the result of the convolution modulo two signals from bit-elements 14 remains constant equal to 1..

JQ In the time diagrams (Fig. 3), it can be seen that if a signal is present in a clock at the input 1 of the analyzer, the signal at the output of block 4 after the arrival of the synJ5 clock pulse does not change its value. At the output of the adder 8 low potential. If in any cycle at the input 1 of the analyzer a logical unit signal appears, then

The 2Q signal at the output of block 4 after the arrival of the corresponding clock pulse changes its value. The outputs of the flip-flops 6 and 7 form signals corresponding to the previous and subsequent values of the signal from the output of block 4. Together with the signal of the logical unit from the output of delay element 12, they provide a low potential

, d at the output of the adder 8.

In the event of any inadequacy that leads to a violation of the described property, the appearance at the output of the adder 8 of the signal is 35

40

This unit coincides in time with the signal from the output of the delay element 13, as a result of which a signal is output at output 10, indicating an analyzer error.

Claims (1)

Invention Formula A signature analyzer containing a signature generator, whose information and synchronization inputs are respectively informational and synchronization inputs of the analyzer, characterized in that, in order to increase reliability by providing self-control, it contains a convolution unit, two moduli , the element And and three elements of delay, the group of inputs of the convolution block modulo two is connected to the group of information outputs of the signature generator, the output of the convolution block by 3 module two is connected to the D-inputs of the triggers, the synchronizing input of the analyzer is connected to the synchronous input of the first trigger, through the first delay element to the synchronous input of the second trigger, and through the second delay element to the first input of the AND element, the second input of which is connected to the output of the result of the adder 2478764 modulo two, the output of the element I is the output of the analyzer error signal, the first and second inputs of the modulo two are connected to 5 outputs of the first and second triggers, respectively, the third input is sum-. modulo two via the third delay element is connected to the information input of the analyzer. PUt.1 (put. 2