SU1226655A1 - Scaling device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automatic monitoring and control systems, for example, in devices for detecting and reading time. The purpose of the invention is to expand the field of application and improve the reliability of reading information. This is achieved by increasing the input frequency with respect to the counting frequency, separating the counting frequency in time, writing information to the register and outputting information to external circuits, and also eliminating the dependence of the length of the read pulse on the counting frequency. The device contains a counter I, register 2, trigger 3, a group of 4 logic elements (LE) I, frequency divider 5, LE And NOT 6, LE And 7, delay elements 8-10, pulse formers 11 and 12, LE OR 13, tires: read 14, input 15, output 16, reset 17, control 18. 1 Cp. f-crystals. 1 il. ja P "GcheE GcheE SZ O) sd ate

Description

The invention relates to a pulse technique and can be used in automatic monitoring and control systems, for example, in devices for detecting and reading time.

The purpose of the invention is to expand the scope and increase the reliability of reading information by increasing the input frequency with respect to the counting frequency, separation of the counting frequency over time, writing information to the register and outputting information to external circuits, and also eliminating the dependence of the read pulse duration on the counting frequency. .

The drawing shows a functional electrical circuit of the scaler.

The device contains counter I, register 2, trigger 3, a group of 4 AND elements, a frequency divider 5, an AND-NE 6 element, an AND 7 element, delay elements 8-10, formers 11 and 12 pulses, an OR 13 element, a bus 14 readout, input bus 15, output buses 16, reset bus 17, control tires 18.

The reset bus 17 is connected to the installation input of the counter 1 to zero, the outputs of which are connected to the information inputs of the register 2, the outputs of which are connected to the first inputs of elements I of group 4, the outputs of elements I of which are connected to output buses 16, the second inputs of elements I of group 4 connected to the output of the delay element 8, the output of the OR element 13 is connected to the input of the zero setting of the trigger 3, the inverse output of which is connected to the first input of the And 7 element, the output and the second input of which are connected respectively to the clock input of the register 2 and c the output of the delay element 9, the input of which is connected to the output of the imaging unit 11 and to the first input of the NAND element 6, the output and the second input of which are connected respectively to the installation input to the trigger unit 3 and to the read bus 14, which is connected to the first input of the OR element 13 and with the input of the delay element 8, the output of which is connected to the second input of the OR element 13. The input of the imaging unit 11 is connected to the input bus 15 and to the clock input of the frequency divider 5, the output of which through the delaying element 10 is connected to the input of the imaging unit 12, connected to a clock input of the counter 1.

The frequency divider 5 is made with a variable division factor, the control inputs of the divider 5 are connected to the control buses 18. With a decadal change in the division factor, a divider 5 can be built by connecting decade counters and a switch in series

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of their outputs using multiplex-1

Elements 8.-10 delays can be performed on passive RC, LC-delay lines or with several repeaters connected in series. The delay of element 8 is chosen equal to the time required for recording information in register 2 and the response time of elements 13.3 and 7. The delay of element 9 is chosen equal to the pulse duration of the driver 11. The delay of element 10 is chosen equal to the response time of elements 11, 6, 3 , 7 and 2 to eliminate the coincidence of the moments of recording information in the register 2 with the transition processes in the counter 1.

Shapers 11 and 12 pulses can be performed, for example, according to the one-shot circuit, which forms a short pulse according to the positive differential of the input pulse. The duration of the pulse generated by the shaper 11, is equal to the duration of the clock pulse required for confident recording in the register 2.

The pulse duration of the driver 12 is equal to the required duration of the clock pulse of the counter 1 used.

In the initial state, the counter 1 is zero, at the outputs of register 2 arbitrary information, the trigger 3 is set to the zero state by the zero level on the bus 14 of the device. By means of the control women 18, the necessary division factor of the divider 5 is established.

The device works as follows.

In the absence of a read signal on the bus 14, the input frequency of the bus 15 is fed to the driver 11, a positive pulse from which through delay element 9 and element 7, and at another input of the second unit the signal of the logical unit from the inverse output of trigger 3 passes to the clock input of register 2, allowing information to be written into it (the first time is zero) from counter 1, counting the pulses from the output of shaper 12, to which the delayed frequency from divider 5 arrives. On buses 16 of the zero information device, as there is no signal read on the bus 14, and inputs the combined elements and Group 4 - a logic zero signal.

With the arrival of the readout signal on the bus 14, when it coincides with the pulse of the imaging unit 11, a logical zero signal appears at the output of the AND element 6, making the installation of the trigger 3 in one state.

The logical zero signal from the inverse output of the trigger 3 prohibits the passage through the element And 7 of the frequency to update the information in the register 2 in the case of a small advance by the read pulse

impulse input frequency or the coincidence of the leading edges of these pulses.

In cases of a read pulse lag from the input frequency pulse, trigger 3 does not change its state, since at the output of element 6, the level of the logical unit is applied to the input of the installation at unit 3 of trigger.

The impulse from the generator 11 through the delay element 8 and the element 7 passes to the clock input of the register 2, in which information from the counter 1 is recorded. By means of the delay element 8, writing to the register 2 ends before the signal of the logical unit appears on the combined signals. inputs of elements And groups 4 and allows the issuance of information from the device.

In the case of a large advance by the pulse of reading the input frequency pulse, the device operates in such a way that the information is written to the register 2 after the end of the reading pulse and the output of information from the device.

Claims (2)

1. A recalculation device containing an input bus, a read bus, a reset bus, a register, a trigger, a group of elements And and a counter, the reset bus is connected to the installation input in "About the counter whose outputs are connected to the information inputs of the register, the outputs of which are connected to the first inputs elements And groups of elements And, outputs of elements And which so10 0 five 0 Dineny with output tires, second inputs of elements AND groups of elements AND are combined, characterized in that, in order to expand the scope of application and increase the reliability of reading information, a frequency divider, an element AND NOT, an element AND, two pulse drivers, three elements are introduced into it delays and the OR element, the output of which is connected to the installation input in “On the trigger, the inverse output of which is connected to the first input of the element I, the output and the second input of which is connected respectively to the clock input of the register and the output of the first element This delay, the input of which is connected to the output of the first pulse generator and the first input of the NAND element, the output and the second input of which are connected respectively to the input of the installation in "1 trigger and read line, which is connected to the first input of the OR element and to the input of the second delay element whose output is connected to the second input of the OR element and the combined second inputs of the elements AND of the group of elements AND, the input of the first pulse shaper is connected to the input bus and the clock input of the frequency divider, the output of which is through t ety delay element coupled to an input of the second pulse shaper whose output is connected to a clock input of the counter. 2. A device according to claim 1, characterized in that the frequency divider is made with a variable division factor, the control inputs of the frequency divider are connected to the control buses.