SU993463A1 - Device for monitoring asynchronous pulse signal alternation sequence - Google Patents

Description

The invention relates to an impulse technique and can be used in automation and computer technology to control pulse sequences. .

A device for monitoring pulse sequences is known, which contains triggers, input and output buses lj.

Closest to the proposed technical entity is a device for controlling the sequence of alternating asynchronous pulses, containing rt. channels with trigger, two input and one output bus in kg1 from channels | 2j.

A disadvantage of the known devices is the low reliability of the control.

The purpose of the invention is to increase the reliability of the control.

The goal is achieved; the fact that the device for controlling the sequence of alternation of asynchronous pulse signals, containing n channels with trigger, two input and one output bus; each channel, a second trigger and a second output bus are entered into each channel, the static K1e installation inputs into O of all the flip-flops are interconnected and connected to the first input bus, the dynamic input setting to 1 of the first flip-flop of each channel except the first one is connected to the forward output of the second trigger, the dynamic input setup in the first trigger and the second output

10 bus previous channel, while in each channel the dynamic input set to 1 of the second trigger is connected to the second input bus, and the dynamic input set to O 15 with the inverse output of the first trigger and the first output bus.

The drawing shows the principal electrical circuit of the proposed device.

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The device contains both channels with triggers 1 and 2 in each channel and 3-5 input and output b and 7 buses.

A device for controlling the sequence of alternating asynchronous pulse signals operates as follows.

The initial state of the device is set by the initial setting pulse.

The 30 states arriving at the static, e inputs of the bus 5 set to O of all triggers, as a result of which the first output tires 6 are set to logical 1, and the second output shing1X7 is set to logical O.

When a series pulse is postponed to the input bus 3 of the first channel, the trigger 1 of the first channel is set to state 1 on the trailing edge of this pulse, zero potential is established at the dynamic input of trigger 2 and the output channel 6 of the first channel.

During normal operation, when a series pulse arrives on the input bus 4 of the first channel. On the rear front of this pulse, the trigger 2 of the first channel goes to one, after which the first channel is reset, the signal from the output bus 7 of the first channel goes to the input bus 3 of the second channel and trigger 1 of the second channel are set to state 1. With the arrival of a pulse on the input bus 4 of the internal channel, the trailing edge of this pulse sets the second channel to its initial state and from its output bus 7 to the input 3 Inu third channel signal is received, triggering the first flip-flop of the third channel, etc. After a pulse arrives at the input bus 4 of the N-th channel, the next pulse arrives at the input bus 3 of the first channel, starting a new cycle of controlling the sequence of alternation of pulses.

If in one of the cycles on the input bus 3 of the first channel is not gfedet. pulse, then the pulse 2 on the input bus 4, the trigger 2 of this channel will be set to one. This state of flip-flop 2 will remain independent of the arrival of the following pulses, on buses 3 and 4 of this channel. As a result, between the output buses 6 and 7 of the first channel, a zero potential difference is established, indicating that there is no impulse in the sequence on the input bus 3 of the first channel.

The indicated state will keep the first channel until the arrival of the initial state pulses on the input buses 5 of all channels. Dialogically, the pulse disappears on the input bus of 3 other channels. and violation of the order of pulse alternation.

Thus, the introduction of new elements and connections in the proposed device allows to increase the reliability of the control compared to the known. In this case, a malfunction signal is issued not only when a controlled sequence of pulsed signals fails, but also if any of the device elements fail.

Claims (2)

Invention Formula A device for controlling the sequence of alternating asynchronous pulse signals, comprising a channel with a trigger, two input and one output bus in each. channels, characterized by the fact that, in order to increase the reliability of the control, a second trigger and a second output are inserted into each channel, the static inputs of the installation in O of all the triggers are interconnected and connected to the first input bus, the dynamic input of the installation is 1 of the first. trigger of each channel except the first one is connected to the forward output of the second trigger, the dynamic input of the installation in the O. first trigger and the second output bus of the previous channel, while in each channel the dynamic 0 installation input in 1 second soy trigger; fault with the second input bus, and dynamic installation input in O with the inverse output of the first trigger and with the first output bus 5 Sources of information taken into account in the examination 1 USSR Author's Certificate No. 680157, cl. H 03 K 5/00, 1977. 2. USSR author's certificate. 491204, cl.: H 03. K 5/18, 1973. XII - TTA ---- I R xfffm / ifml .Xl. one five  set of § 7