SU1285476A2 - Device for checking logic circuits - Google Patents

Abstract

The invention is devoted to computing, in particular to the means of monitoring and debugging digital devices, and is an improvement of the invention according to the author No. 744580. The purpose of the invention is to increase the reliability of the control. For this purpose, a short pulse duration detection unit and a switch are entered into the device for controlling the logic circuits. The proposed device can be used to monitor and diagnose faults in devices of digital computing and discrete automation. 3 il.

Description

The invention relates to computing, in particular to means of monitoring and debugging digital devices, and is an improvement of the invention according to the author. St. No. 744580.

The purpose of the invention is to increase the reliability of the control.

FIG. 1 shows a block diagram of the device; FIG. 2 is a functional block diagram of the registration of pulses of short duration; FIG. 3 shows a time diagram of the operation of the device in the analysis mode of logical time diagrams.

The device contains a block of 1 registration of pulses of short duration switch 2-, register 3, digital comparator 4, block 5 of delay, block 6 of memory, first block 7 of control, second block 8 of control, block 9 of indication, generator 10 of clock pulses , synchronization unit 11, a 12-code transformer, a time diagram generation unit 13, a sign information generation unit 14, information inputs 15 and 16 of the device, and an external synchronization input 17.

The block of registration of pulses of short duration (Fig. 2) contains triggers 18-23, switch 24, element OR 25, element NOT 26, clock input 27, outputs 28 and 29. Triggers 18, 20 and 19, 21 form the first and second drivers, respectively 30 and 31,

The device operates in two modes - the mode of analysis of logical states and the mode of analysis of logical time diagrams.

In the analysis mode of logical time diagrams, the device operates as follows.

When the slider switch 2 is installed in the lower position, information input 15 is connected directly to the corresponding input of register 3. In this case, the device steadily records signals whose duration exceeds the sampling time ut determined by the speed of memory block 6 and set by the clock frequency of the generator 10 clock pulses PT C (frequency of entry of information on the register 3). In the event that in the sequence of pulses under study there are such, the duration of which is less than

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above the sampling time (t), the circuit cannot provide guarantees} P1 their registers, we on register 3 and in block 6 of memory (Fig. 3).

When the slider switch 2 is set to the upper position, the first input of the register 3 is disconnected from the information input 15 and connected to the output of the short-duration pulse detection unit 1.

When a single pulse of short duration (t - L t) arrives, the shaper 31, consisting of flip-flops 19 and 21, is triggered. At the same time, the shaper 30, made up of flip-flops 18 and 20, is blocked by a low level signal from the output of the flip-flop 21 the duration during the next clock cycle of the clock generator, shaper 30, consisting of the flip-flops 18 and 20 (Fig. 3), is triggered,

Thus, the first and second inputs of the OR 25 element are either given a single signal with a duration equal to it (in the presence of a single pulse of short duration), or a pack of similar pulses (provided that the total duration of the packet is less than ut) (Provided that the burst width is within the duration of the n periods of the clock frequency F-pQi of the clock generator) Depending on the position of the slider 24 of the switch, two options are possible for the pulse duration detection unit awes

In the lower position of the slider switch 24 with the help of the element OR 25, the impulses formed by the triggers 20 and 21 are superimposed on the sequence of signals under study. In this case, either pulses from the formers 30 and 31 of block 1 are recorded in the device, which are reproduced in the time diagram as separate signals of the duration fit (n-ut) —on the arrival of pulses of short duration (packs of pulses of short duration), or signals of the input sequence provided that their duration exceeds bt. Triggers 22 and 23 serve to eliminate the temporal mismatch of the fronts of the input signals with the fronts of the pulses generated by triggers 20 and 2 1.

In the upper position of the slider of the switch 24 at the output of the element OR 25, either a pulse of length At is formed, corresponding to the appearance of any front in the signal sequence being studied, or a pulse of the duration corresponding to the appearance of a batch of pulses of short duration or splitting of the front of the signal under investigation

the triggers are connected respectively to the inverse outputs of the fourth and fifth triggers, whose information inputs are connected to the direct exits of the first and second triggers, respectively, the synchronous inputs of the third, fourth, fifth and sixth triggers are combined and connected to the output of the HE element whose input is connected fO with the generator clock output of the device, the information input of the first trigger is connected to the forward output of the fifth trigger, the information

The analysis of the studied sequences — the input of the second trigger — is the bus of the signal signals when the potential of a logical unit is multiplied by the product of the recorded time of the pulse registration unit of the mannose diagram on the screen of block 9, the duration is information input

indications

Claims (1)

Claim 20 A device for controlling logic circuits according to aut. St. No. 744580, characterized in that, for the purpose of increase the reliability of the control, a pulse duration detection unit and a switch are entered into it, a short duration pulse detection unit contains six triggers, an OR element, a NOT element and a switch, and in the short duration pulse detection unit the first and second trigger inputs and the third information input the trigger is combined and connected to the first information input of the device, the zero inputs of the first and second  and the output of the sixth trigger are connected respectively to the second information the device’s first input and the first closing contact of the device’s switch, the second closing contact of which is connected to the output of the OR element of the small pulse detection unit duration, the first and second inputs of the OR element are connected to the outputs of the fourth and fifth triggers, respectively, the output of the third trigger is connected via a switch to the third input of the OR element, the circuit breakers of the device switch are connected to the first and second information inputs of the device, the switching contacts of the device switch are connected with the corresponding informational 1st register entries. Fy Jit ShoZ V.OZ, .. p.o guts JSCHJCHNNCHSCHCHCHCHCHSCH lISShSh Record to register - | I | I 1 1 I I | | I I I I I I I I I I I I I I 1 I I I I I I I 1 1 I I I I I I I I I I I I Investigated after -HU tu aovap e nos m -JM l shsh ul, yg / 5fib ;; (o5 trigger 21 trigger output 20 n P The first BiiiMS register 3 (Perekpachagpel 2 in the bottom position) neisBbiu register output 3 (switch g 8th / g polo; hz; switch Hz to bottom: pos. The first output of the register 3 (switches Zu Z4 In the upper position) Fig.Z Fig.Z