SU1059550A1 - Device for trouble tracing - Google Patents

Abstract

.STREAM FOR SEARCHING FOR UNIS-GRAINS, containing serially connected register and display unit, interface elements, whose information inputs are device inputs, and outputs are connected to the installation inputs into the unit of the corresponding triggers that differ from the goal is to increase its reliability by eliminating information signals, a multiplexer is entered into it, the first and second elements AND, the element NOT, the counter and the clock pulse generator, the output of which is connected to the input of the counter. NT NOT - to the first input of the first element I, the outputs of the counter are connected to the corresponding information inputs of the register, the second element I and the address inputs of the multiplexer, whose information inputs are connected to the outputs of the corresponding 1x triggers, and the output the output of which is connected to the gate (General input of the register, the output of the second element AND is connected to the inputs of the installation to zero of the triggers and to the control. interface inputs.

Description

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IUD

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The invention relates to the automatic control of the health of electronic devices and can be used to search for failures in devices with relay fault signals.

A troubleshooting device is known that allows automatic troubleshooting to include electronic keys, first inputs connected to sensors, a multiple input mode OR, output connected to the first one-digit inputs of the shift register, time relay, triggers, zero inputs connected to the inputs of electronic keys, the second the inputs of which are connected to the output of the time relay, the elements of the time delay, the outputs connected to the single inputs of the trigger, sequentially connected two-input c we are OR, BANCHES, signaling inputs connected to the zero outputs of the flip-flops and to the second inputs of two-input circuits OR, a driver, the input connected to the output of the multi-input circuit OR, and the output to the input of the time relay, and the address coder, the outputs of the red terminal are connected to the second ones one by one inputs to the zero output of the first trigger, to the inhibit input of the first BAN circuit and to the first input of the two-input OR circuit, other inputs to the corresponding inputs of the delay elements and the outputs of the BAN circuit, -rotating inputs are connected to the outputs of two-input OR circuits l.

The disadvantages of this device are low reliability and noise immunity, as well as its complexity.

The closest to the present invention is a device for searching for faults, containing sensors of relay signals, serially connected elements OR, triggers, the installation input of each of which is connected to the output of the corresponding delay element, and the output through the BANNER element to the input of the encoder, the outputs of which are through the register connected to the display unit, controlled selectors, the first input of each of which is connected to the corresponding sensor of the relay signals, and the output - to the information input of the corresponding a trigger, an additional OR element, the output of which is connected to the second inputs of the controllable selectors and the second inputs of the register, and the inputs to the outputs of the corresponding, trigger and element OR.

A disadvantage of the known arrangement is low reliability, since it allows the encoder to arrive at the inputs simultaneously.

two or more alarms from. sensors.

The purpose of the invention is to increase the reliability of the device by eliminating the races of the signals from the sensors. 5 The goal is achieved by the fact that the multiplexer, the first and the first, and the device for troubleshooting, containing serially connected register and display unit, interface elements, information inputs of which are device inputs, and outputs are connected to the installation inputs in the unit of the corresponding triggers the second element and, the element NOT, the counter and clock generator, the output of which is connected to the input of the counter and through the element NOT to the first input of the first element I, the outputs of the counter

Q connections with the corresponding information inputs of the register, the second element And the address inputs of the multiplexer, the information inputs of which are connected to the outputs of the corresponding triggers, and the output 1D to the second input of the first element And, the output of which is connected to the strobe submission of the register, the output of the second element And connected to the inputs of the installation to zero of the triggers and to

0 control inputs of mates.

The drawing shows a block diagram of the proposed device.

five-. The device contains interface 1, multiplexer 2, counter 3, generator 4 clock pulses, first element 5, register b., Display unit 7, element 8, trigger 9 and second element 10, sensors 11.

The output buses of the sensors of the signals of the faults of the sensors 11 are connected to the first inputs of the coupling elements 1. Elements 1 are designed to suppress interference to the device input.

Multiplexer 2 is intended for alternately switching signals from information inputs to output. Address

0 of the switched input is determined by the code arriving at the address inputs of multiplexer 2..

The triggers 9 are used to store the fault signals from the sensors 11 of the respective monitored units during one cycle of polling the states of the sensors 11 and ensure the fixation of short-term failures, the duration of which

0 is less than one polling cycle time. The second element 10 is designed to return the flip-flops 9 to the initial state at the end of each polling cycle of the states of the sensors 11 of the controllable blocks. Register 6 is intended to record and temporarily store the address code of the faulty block. . The display unit 7 is designed to indicate search results as well as to classify failures on stable and unstable determinations and to give out their frequency of occurrence. Element HE 8 provides input of the address code of the faulty unit to register b in the interval between the clock pulses of the generator 4 when the transients in the device end . The device works as follows. The counter 3, under the action of clock pulses arriving at its input from the generator 4 output, generates at its outputs a cyclic sequence of binary equivalents of decimal numbers from zero, the conversion factor of counter 3 is equal to the number of information inputs of the multiplexer 2. The binary code from the outputs of counter 3 is fed to the inputs of register b and the address inputs of the multiplexer 2. Multiplexer 2 cyclically 4mutes the signals from its information inputs sequentially from first to last to the output. The address of the information input of the multiplexer 2, which is determined every clock cycle, is determined by the binary code at its address inputs. From the output of multiplexer 2, the signal arrives at the first input of the first element I 5 which is closed for the duration of the current pulse by a zero signal arriving at its second input from the output of the element NO 8. In the interval between the clock pulses, a single signal from the output of the element HE 8 opens element 5 and the signal from the output of multiplexer 2 through element 5 is fed to the second register inputs. In the absence of fault signals from sensors 11 monitored blocks, the information inputs of multiplexer 2 are in zero state and the inputs are Istra 6 closed. In case of failure of several monitored blocks, single signals from the corresponding Sensors 11 are fed to the first inputs of elements 1, which select the input signal by amplitude and duration, which makes it possible to eliminate interference to the input of the device with parameters different from the guaranteed parameters of the useful input signal. The signals from the outputs of the corresponding elements arrive at the information inputs of the corresponding triggers 9, and set them to a single state. Single signals from the trigger outputs go to the corresponding information inputs of multiplexer 2. When polling the corresponding input of multiplexer 2, a single signal from its input switches to the output and through element 5 goes to the second inputs of register 6, allowing the address code of the faulty block to be written. From the output of register b, the address code of the faulty unit is fed to the display unit 7 to indicate the search result, to be recorded in the memory of the display unit 7, to further classify failures as steady and unstable and to determine the frequency of occurrences. OE) the block fault address codes are removed during each polling cycle of the information inputs of multiplexer 2. The polling frequency of the polling cycles is directly proportional to the clock pulse frequency of generator 4. At the end of each polling cycle, the inputs of multiplexer 2 are generated single signals, the second element 10 triggers and sets the flip-flops 9 to the zero state with a short pulse, the elements 1 close for the duration of the pulse. The proposed device makes it possible to get rid of information signaling races by separately polling them with a multiplexer, which. increases reliability.

Claims (1)

(5 7) DEVICE FOR TROUBLESHOOTING, which contains series-connected register and display unit, interface elements, information inputs of which are device inputs, and outputs are connected to the unit inputs to the unit of corresponding triggers, characterized in that, in order to increase it reliability by eliminating the racing of information signals, a multiplexer, the first and second AND elements, the NOT element, a counter and a clock pulse generator, the output of which is connected to the counter input and through the NOT element to the first input of the first AND element, the outputs of the counter are connected to the corresponding information inputs of the register, the second AND element and to the address inputs of the multiplexer, the information inputs of which are connected to the outputs of the corresponding triggers, and the output to the second input of the first AND element, the S output of which is connected to the gate by the input of the register, the output of the second ΙΖΛ element AND is connected to the inputs of the zero setting of the triggers and to the control inputs of the interface elements. | > there may be bounce signals