SU1383367A1 - Device for checking compare circuits - Google Patents

Abstract

The invention relates to automation and computing and can be used in the development of tools for checking electronic components of discrete automation and computing. The aim of the invention is to simplify the device. A device for controlling comparison circuits contains a controlled comparison circuit 1, the first 2 and second 3 counters, the error signal generation unit 4, the first 5, the second 6 and the third 7 triggers, the pulse generator 8, AND 9 element, OR 10 element, start input 11 and output 12 error signal. I zp f-ly, 1 nl.

Description

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The invention relates to automation and computing and can be used in the development of tools for checking electronic components of discrete automation and computing.

The purpose of the invention is to simplify the device.

The drawing shows a functional diagram of the device.

A device for controlling comparison circuits contains a controlled comparison circuit 1, the first 2 and second 3 counters, the error signal generation unit 4, the first 5, the second 6, the third 7 triggers, the 8 clock pulse generator, AND 9 element, OR 10 element, start II input and output 12 device errors. In addition, the error signal generation unit 4 contains a decimator 13, a multiplexer 14 and an AND element 15, inputs 16-18 and outputs 19-21 of the decoder 13.

The controlled comparison circuit 1 provides a comparison of two P-bit binary numbers (A and B) and generates a single signal at the first output, if, or a single signal at the third output 18, if. At the second output, a single signal is generated if A is B.

Counters 2 and 3 are designed to form binary numbers A and B, respectively, supplied to the comparison circuit 1. An increase in the content of each of the counters 2 or 3 per unit occurs when a clock pulse, generated by the pulse generator 8, arrives at their counting inputs, if a single signal is present at the input V of the counter at this time.

The error signal generation unit 4 serves to generate an error signal at the output 12 of the device, if the comparison circuit being monitored produces an incorrect result. He works in the following way. The decoder 13 generates at its outputs 19-21 the signals described by logical expressions

 aieaiyais;

220 Sieaiyais;

X2I aieaiyais.

Multiplexer 14 implements a logical function.

X5X6Z20 + X5X6Z20 + X5X6Zi9 + X5X62: 2b

where H5Hb - the signals taken from the inverse outputs of the flip-flops 5 and b, respectively. Thus, it follows from the above logical expressions that if A B, then when the comparison circuit 1 is working correctly, a single signal is generated at the output 20 of the decoder 13, which arrives at the output of the multiplexer 14 and closes the And 15 element. As a result, the next clock pulse from the generator output 8 does not pass to the device output 12 and no error signal is generated. With any other combination of signals at the outputs of the comparison circuit 1 at the output 20 of the decipher0

To torus 13 there is a zero signal, element 15 is open and a clock pulse passes to output 12 of the device, signaling the malfunctioning of the comparison circuit 1.

Similarly, the block works

generating error signals at or. In these cases, the ayushi signal is forbidden to the inverse input of the element 15, only when a single signal is formed at the corresponding output of the comparison circuit 1, and there are no single signals at its other outputs.

Trigger 5 controls the switching of trigger 6 and generates a control signal to one of the control inputs of multiplexer 14.

Trigger 6 controls the operation of counters 2 and 3 and generates a control signal to another control input of multiplexer 14. Triggers 5 and 6 are counting triggers and switch to the opposite state on the falling edge of each pulse arriving at their counting inputs.

The trigger 7 is designed to start - stop the operation of the device. It switches to one state when a pulse arrives at input 11 of the device and returns to its initial state either by an overflow signal generated by a counter 2 at the end of the monitoring cycle, or by an alarm signal 01 generated by an error signal generation unit 4 0. The element OR 10 is used to combine these signals to the input R of trigger 7.

The generator 8 generates a sequence of clock pulses of 1 pulses, ensuring the operation of the device. It starts at a single signal at the input and stops when trigger 7 returns to its initial state.

Element And 9 controls the passage of clock pulses to the counting input of trigger Q of trigger 6. It opens only at the zero state of trigger 5, therefore only odd clock pulses are passed to the input of trigger 6.

The device for controlling the comparison circuits works as follows. 5 In the initial state, all memory elements are at zero. Circuit installation circuit elements in the initial state conventionally not shown.

After the signal "Start at 0, input 11 of the device, trigger 7" switches to one state and starts the generator 8 pulses, which begins the formation of a sequence of clock pulses.

The first clock pulse passes to the input of the element 15. If a single signal is present at the second output of the controlled comparison circuit 1, it does not pass through the element 15 and the error signal on

the output 12 of the device is not formed. At the same time, this clock pulse travels to the counting inputs of triggers 5 and 6 and counters 2 and 3. As a result, triggers 5 and 6 are switched to one state, one is recorded in counter 3, and counter 2 remains in the initial state, since V of this counter signal is zero. The numbers,, (i.e.) arrive at the inputs of the controlled comparison circuit 1, and at its output there appear signals, O (if correctly operated).

The second clock pulse arrives at the input of the element And 15 and with the correct signals at the outputs of the comparison circuit 1 to the output 12 of the device does not pass. At the same time, it enters the inputs of the counters 2 and 3 of the trigger 5. As a result, one is recorded in the counter 2, and the trigger 5 returns to the zero state. At the inputs of the comparison circuit 1, a pair of numbers is formed.

The third clock pulse polls the output of the error signal generation unit 4, switches trigger 5 to a single connection, and trigger 6 switches to zero. The number A 2 () is recorded in counter 2.

On the fourth clock pulse, the triggers 5 and 6 are set to zero, numbers are recorded in counters 2 and 3, and the output signals of the comparison circuit 1 are checked for correctness.

Further, the process of control of the comparison circuit 1 repeats cyclically with increasing numbers A and B by one in a similar sequence: A B, A, B, A B ... until the counts A are set in counters 2 and 3 where n is the width of the comparison circuit 1.

After this, the next clock pulse checks the correctness of the response of the comparison circuit 1 to the numbers А В 2 and passes to the output of the overflow of the counter 2 and then through the element OR 10 to the R input of the trigger 7. The latter returns to the initial state.

If, in the control process, at least one of the pairs of numbers A and B of comparison circuit 1 produces an incorrect result, an error signal is generated at the device input 12, which is fed to the R-trigger of trigger 7, and the control process of the comparison circuit 1 is stopped.

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Claims (2)

1. Device for control of comparison circuits, containing a clock pulse generator, first trigger, OR element, AND element, an error signal generation unit whose output is the error output of the device and connected to the first input of the OR element whose output is connected to the zero input of the first trigger The single input of which is the device start input, the output of the first trigger is connected to the start input of the clock generator, the output of which is connected to the enabling input of the error signal generation unit and first in And, the information inputs of the device for connecting to the outputs "Equal to," More "Less controlled circuit form the first group of inputs of the error signal generation unit, characterized in that, in order to simplify the device, it contains the second and third triggers, the first and second counters , groups of outputs of which are respectively the first and second groups of inputs of the device for connection to the first and second groups of inputs of the monitored circuit, the overflow output of the first counter is connected to the second input of the OR element The output of the clock generator is connected to the counting inputs of the first and second counters, the second trigger, the inverse output of which is connected to the second input of the element I, the output of which is connected to the counting input of the third trigger, the direct output of which is connected to the resolution input of the first counter, and the inverse output - with the enable input of the second counter, the inverse outputs of the first and second triggers form the second group of inputs of the error signal generation unit. 2. The device according to claim. {The fact that the signal conditioning unit contains a decoder, multiplexer and element, the first group of inputs of the error signal generation unit is connected to the inputs of the decoder, the outputs of which are connected to the information inputs of the multiplexer, the second group of inputs of the formation unit an error signal is connected to a group of address inputs of an im, a multiplexer, the output of which is connected to an inverted input of an element i, the direct input of which is the enable input of an error signal generating unit, an output Coping and is the output of the unit's block.