SU1499490A1 - Pulse repetition rate divider with variable pulse duration - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation devices for producing a series of clock pulses. The purpose of the invention is to expand the functionality. The goal is achieved by controlling the elements of comparison. The device provides the ability to switch to the self-blocking mode in case of failures in the operation of the first or second code comparison elements. In this case, the generation of incorrect output information is stopped, and a single error signal is established on the control bus. The device contains a pulse counter 1, elements 2, 3 and 14 comparison codes, triggers 4, 10 and 11, output buses 5 and 6, element AND 7, elements OR 8 and 9, output bus 13, control bus 13, code buses 15, 16. In addition, the divider contains the element EXCLUSIVE OR 17, the elements OR 18, 19 and 20, the switch 21. 1 Il.

Description

15

13

four

CD CD 4

CD

The invention relates to a pulse technique and can be used in automation devices before receiving a series of clock pulses.

The aim of the invention is to enhance the functionality by allowing control of the elements of comparison,

The device provides a POSSIBLE-JQ house of the first trigger 4, reset input

15

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The transition to the self-blocking mode in the case of the incorrect operation of the first IP of the second code comparison element, while the generation of incorrect output information is stopped, and a single error signal is set on the control bus.

The drawing shows an electrical functional divider circuit.

Pulse frequency divider with adjustable pulse duration contains a pulse counter 1, the outputs of which are connected to. the first groups of inputs of the first 2 and second 3 elements of the comparison are CO- DO.V, the first trigger 4., the inverse and direct outputs of which are connected respectively to the first 5 and second 6 output buses, element 7, first 8 and second 9 elements OR, the second and third triggers 10 and 11, the input bus 12 and the control bus 13, which is connected to the direct output of the second trigger 10, the inverse output of which is connected to the first input of the element And 7 whose code is connected to the counting input 1 of pulses, the second input - input bus 12 and the clock input of the second trigger 10, input trigger which is connected to the output of the second element. OR 9, the first input of which is connected respectively to the output of the Greater than t: network element 14 of the comparison code, the second input to the output of the first element OR 8 and the reset input. the third trigger 11, the inputs of the first element OR 8 are connected to the same outputs of pulse counter 1, the reset input of which is connected to the reset input of the first trigger 4, and the first and second group of inputs of the third code comparison element 14 are connected respectively to the first and second code buses 15 and 16 In addition, the divisor contains the element SKIPCHUCH1 1EE OR 17, the third 18, the fourth 19 and the fifth 20 elements OR, and the switch -21, the first and second

groups of inputs of which are connected respectively to the first 15 and second 16 code buses, the group of outputs is connected to the second groups of inputs of the first 2 and second 3 code comparison elements, and its control input is connected to the information input of the third trigger 11 and direct output,

and the start of which is connected to the outputs of the fourth 19 and fifth 20 elements OR, respectively, the first inputs of which are connected respectively to the inverse and direct inputs of the third trigger 11, the input of the fourth element OR 19 is connected to the output of the second element 3 of the code comparison and the first inputs of the third element OR 18 and the EXCLUSIVE OR 17 element, the second input of the fifth element OR 20 is connected to the output of the first code comparison element 2 and the second inputs of the third element

25 or 18 and the EXCLUSIVE SHSh 17 element whose output is connected to the information input of the second trigger 10, and the output of the third element OR 18 is connected to the clock input of the third

30 trigger 11 „

A pulse frequency divider with adjustable pulse duration works as follows. In the initial state, the counter 1 is named

5 pulses are reset, at the output of the first 2 and second 3 comparison elements - high levels, on the input bus 12 - low level, the first 4, the second 10 and the third 11 triggers are reset,

40 of the first 15 and second 16 code buses set codes corresponding to the values of the duration and period of the output 1 {mpuls, and the code value on the second bus 16 exceeds

45 code value on the first bus 15, on the output bus 13 of the control - the zero level. The zero level from the direct output of the first trigger 4, acting on the control input of the switch 21, passes on its output the code value set on the first code bus 15,

The clock pulses arriving at the input bus 12 pass through the element AND 7 and the pulse counter 1 is triggered, which counts them. With the coincidence of the codes at the output of the pulse counter 1 and the first code bus 15, the first 2

50

the house of the first trigger 4, reset input

groups of inputs of which are connected respectively to the first 15 and second 16 code buses, the group of outputs is connected to the second groups of inputs of the first 2 and second 3 code comparison elements, and its control input is connected to the information input of the third trigger 11 and direct output,

and the start of which is connected to the outputs of the fourth 19 and fifth 20 OR elements, respectively, the first inputs of which are connected respectively to the inverse and direct inputs of the third trigger 11, the input of the fourth element OR 19 is connected to the output of the second element 3 of the code comparison and the first inputs of the third element OR 18 and the EXCLUSIVE or 17 element, the second input of the fifth element OR 20 is connected to the output of the first code comparison element 2 and the second inputs of the third element

or 18 and EXCLUSIVE SHSh 17, the output of which is connected to the information input of the second trigger 10, and the output of the third element OR 18 is connected to the clock input of the third

trigger 11 „

A pulse width following frequency divider with adjustable pulse duration works as follows. In the initial state, the pulse counter 1 is reset, the output of the first 2 and second 3 elements of the comparison is high, the input bus 12 is low, the first 4, the second 10 and the third 11 triggers reset on

the first 15 and second 16 code buses are set up with codes corresponding to the duration and period of the output 1 {mpuls, and the code value on the second bus 16 exceeds

the code value on the first bus 15, on the output bus 13 of the control is zero. The zero level from the direct output of the first trigger 4, acting on the control input of the switch 21, passes on its output the code value set on the first code bus 15,

The clock pulses arriving at the input bus 12 pass through the element AND 7 and the pulse counter 1 is triggered, which counts them. With the coincidence of the codes at the output of the pulse counter 1 and the first code bus 15, the first 2

and the second 3 elements of the comparison codes (in case of their serviceability) produce low levels, the elements EXCLUDING OR 17 entering the inputs, the output of which continues to remain zero. Therefore, at the direct output of the second trigger 10, and thus on the control bus 13, there is a zero level, which signals the correct operation of the first 2 and second 3 elements of the comparison of the device codes.

V At the same time, the zero level from the output of the first comparing element 2, affecting the second input of the fifth element OR 20, will form at its output a zero level at which the first trigger 4 is set to one state. The change of state at the output of the first trigger 4 causes to the formation of a single-level signal at its direct output, which, acting on the control input of the switch 21, passes at its output the code value set on the second code bus 16, resulting in the output of the first 2 and second 3 el code comparison items are formed in single levels. The unit level from the direct output of the first trigger 4 enters the D input of the third trigger 11. V. time of the formation of a positive differential at the output of the third element OR 18 (when the input of its single signals from the outputs of the first 2 and second 3. elements, comparing codes, the third .trigger 11 is set to a single average value, the unit level from the direct output of which, affecting the S input of the first trigger 4, does not change the state of the latter,

At the moment of coincidence of the code value at the output of the pulse counter 1 with the code on the second code bus 16, the first 2 and second 3 code comparison elements are triggered and low levels are generated (if they are operational) that do not cause, as in the first, bus 13 control of the alarm signal of a single level, which indicates the correct operation of the first 2 and second 3 elements of the comparison of the device codes. Simultaneously zero level from the second element 3

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comparing the codes, acting on the second input of the fourth element OR 19, forms at its output a zero level, by which the first trigger 4 is set to the zero state. The change of states at the output of the first trigger 4 leads to the formation of a zero level signal at its direct output, which, acting on the control input of the switch 21, passes on its output the code value set on the first code pin 15, resulting in the output of the first code pin 15 2 and the second 3 elements of the code comparison, unit levels are formed. In this case, the zero level from the direct output of the first trigger 4 enters the D input of the third trigger 11 and at the time of forming a positive differential at the output of the third element OR 18 (when posting to its inputs single signals from the outputs of the first 2 and second 3 elements code comparison, the third trigger 11 is set to one

Thus, pulses are formed on the first 5 and second 6 output buses, the period and duration of which are determined by the values of the binary codes on the first 15 and second 16 code buses, respectively.

When installing on the first code bus 15 a binary code value that exceeds or equal to the value of the binary code on the second code bus 16; at the output of More than the third reference element 14, forms a low level, which at the time of zero pulse counter 1 generates a low level at the output of the second element OR 9, which sets the second trigger 10 into a single state,

g At the same time, a high level is generated on the control bus 13, indicating that the input code is incorrect on the first 15 and second 16 code buses, and a low level from the inverse output of the second trigger 10 blocks the clock pulses to the counting input of the counter 1 pulses.

Thus, the divider provides for the possibility of switching to the self-blocking mode in case of incorrect operation of the first or second code comparison elements, while the generation of an incorrect output formation is stopped (and on the busbar

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control is set to a single error signal

Claims (1)

Formula inveni.ni Pulse-following frequency divider with adjustable pulse duration, containing a pulse counter, a group of outputs of which is connected to the first groups of inputs of the first and second elements C1 of the first codes, the first trigger, inverse and direct outputs of which are connected respectively to the first and second output buses, the element And, the first and second elements of the RSHI, the second and third triggers, the input bus and the control bus, which is connected to the direct output of the second trigger, the inverse output of which is connected to the input input of the AND element, you the stroke is connected to the counting input of the pulse counter, the second input is connected to the input bus and to the clock input of the second Trigger, the start input of which is connected to the output of the second OR element, the first input of which is connected respectively to the output of the Third comparison code element, and the second input - with the output of the first OR element and with the input of the third trigger, the inputs of the first OR element are connected to the same outputs. pulse counter, the reset input of which is connected to the reset input of the first- isoro trigger, and the first and second groups of inputs of the third element five 0 five 0 five The codes are connected to the first and second code buses, respectively, characterized in that, in order to extend the functionality by enabling control of the function of the code comparison elements, the EXCLUSIVE OR element, the third, fourth and fifth SHS elements, the switch, the first and Vrtra groups of inputs are connected respectively to the first and second code buses, a group of outputs connected to the second groups of inputs of the first and second code comparison elements, and its control input is soy Inen with the information input of the third trigger and the direct output of the first trigger, the reset and start inputs of which are connected to the outputs of the fourth and fifth OR elements, respectively, the first inputs of which are connected respectively to the inverse and direct outputs of the third trigger, with the output of the second comparison element and with the first inputs of the third OR element and the EXCLUSIVE OR element, the second input of the fifth SHW element is connected to the output of the first comparison element of the coder and the second inputs The third element OR and the EXCLUSIVE OR element, the output of which is connected to the information input of the second trigger, and the output of the third element OR is connected with clock input of the third trigger. I