SU1406718A1 - Frequency-phase detector - Google Patents

Abstract

The invention relates to radio engineering and automation, and b. Used in the device .x automatic frequency and phase adjustment. The purpose of the invention is to improve accuracy. The frequency-phase detector contains four D-flip-flops 1, 2, 3, and 4, element 5 EXCLUSIVE OR, two diodes 11 and 12, and an integrating link 13. The goal is achieved by introducing into the device the second element 6 EXCLUSIVE OR and four resistors 7, 8, 9 10. The introduction of these elements makes it possible to obtain a device that pea guides the phase mismatch of the signal. SE in case of equality of their frequency. If the delay of pulses at the input of the D-flip-flop 3 relative to the signal at the input of the D-flip-flop 1 is more than half of the pulse following period, the output of element 5 is dominated by high signal levels, and at the output of element 6 - low levels, 3 or less.

Description

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The invention relates to radio engineering and automation and can be used in devices for automatic adjustment of frequency and phase.

The purpose of the invention is to improve accuracy.

FIG. 1 shows a circuit diagram of a frequency-phase detector; in fig. 2 and 3 - stress diagrams.

The frequency-phase detector contains four D-flip-flops I, 2, 3, and 4, the first and second elements EXCLUSIVE OR 5 and 6, four resistors 7, 8, 9, and 10, two diodes 11 and 12, and an integrator 13.

Frequency-phase detector works as follows.

The C-inputs of D-flip-flops receive pulse sequences of two compared frequencies, while periodically with a difference frequency there are situations when two fronts of another frequency pass between two edges of pulses of one frequency. The voltage plots for the case when the frequency at the input of the D-flip-flop 1 is higher than the other at the input of the D-flip-flop 3 is shown in FIG. 2 a, b. The signal at the input of D-flip-flop 3 switches it regularly (Fig. 2g), and the signal at the input of D-flip-flop 1 — at the moment of two fronts between two fronts at the other input and leaves flip-flop 1 in the previous state (FIG. 2 a). At the outputs of the EXCLUSIVE OR elements 5 and 6, the signals shown in FIG. 2nd and d, respectively. In this case, on D-flip-flop 2, a situation arises when the signal front at the C-input corresponds to a low signal level at the O-input, D-flip-flop 2 is set to the logical state "O, and the next pulse returns to its initial state, and Inverse.m. the output of D-flip-flop 2 produces positive pulses (Fig. 2 g), which follow with a difference frequency and duration equal to the period of the input signal fed to D-flip-flop 1 at the output of D-flip-flop 4 (Fig. 2 and).

The pulses from the inverse output of the D-flip-flop 2 are fed through the first diode 11 and the resistor 9 to the input of the integrator 13, at the output of which the positive potential of fig. 2 k.

In case of equality of the parts (fig. Za, b), the frequency-phase detector switches to the phase comparison mode (fig. Sv, d). At the outputs of the elements EXCLUSIVE OR 5

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and 6, signals are formed (Fig. 3e, d), the ratio between the high and low levels of which is proportional to the phase mismatch between the input signals. If the delay of the pulses at the input of the D-flip-flop 3 relative to the signal at the input of the D-flip-flop 1 is more than half the pulse tracing period, the output of the EXCLUSIVE OR 5 element is dominated by high signal levels, and at the output of the EXCLUSIVE OR 6 element - low levels. These signals through the resistors 7 and 8 are fed to the inputs of the integrator, the output of which is set to a positive level (Fig. 3k). In this mode, D-triggers 2 and 4 are in zero computation (Fig. 3 g, i).

Claims (1)

Invention Formula A frequency-phase detector containing four D-flip-flops, C-inputs of the first and second D-flip-flops combined, C-inputs of the third and fourth D-flip-flops combined and are the inputs of the frequency-phase detector, the direct output of the third D-flip-flop is connected to D-c) by the iod of the first D-flip-flop and the first input of the EXCLUSIVE OR element, the inverse output of the first D-flip-flop is connected to the D-input of the third D-flip-flop and the second input of the EXCLUSIVE OR element, whose output is connected to the D-input of the fourth D-flip-flop, two diodes and an integrating link, characterized in o, in order to increase accuracy, a second EXCLUSIVE OR element and four resistors are introduced into it, and the direct outputs of the first and third D-flip-flops are connected to the corresponding inputs of the second element EXCLUSIVE OR, the output of which is connected to the D-input of the second D-trigger, inverse the output of which is connected to the anode of the first diode, the cathode of which through the first resistor is connected to the first input of the integrator and one output of the second resistor, the other output of which is connected to the D input of the fourth D-flip-flop, the inverse output of which is Connected to the anode of the second diode, the cathode of which is connected to one output of the third resistor, the other output of which is connected to the second input of the integrator, the output of which is the output of the frequency-phase detector, and the fourth resistor, the other output of which is connected to the D input of the second D- trigger I I I I I I b a p n 1G e and-and-I J1 P P P1 IP. Well and to I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I d Jl rLJlJlJLJLJl Jl ri lJl-Jl e irinj ririJnJTnJ LJnjnjnjnjnj I I I I I I I FIG. 2