SU1741256A1 - Device for automatic sensitivity control of receiver - Google Patents

Abstract

Use: radio engineering, radio receivers for various purposes. SUMMARY OF THE INVENTION: A device for automatically adjusting the sensitivity of a receiver comprises an adjustable attenuator 1, a passband modulator 2, a linear path 3, an amplitude detector 4, a comparison element 5, a pulse generator 6, 2 keys 7.8, a clock pulse generator 9, a time selector 10, counter 11, decoder 12, Schmidt trigger 13, 3 inverters 14,15,22, 3 coincidence elements 16, 17, 18, D-flip-flop 19, delay element 20, OR element 21, 2 low-pass filter 23,24. The aim of the invention is to increase the sensitivity adjustment sensitivity, which is achieved due to the formation of controlled voltage at the output of the reference element 5 using a passband modulator 2 and switched low-pass filters 23.24. 2 Il. SP

Description

The invention relates to radio engineering and can be used in receiving devices.

Devices are known to improve the multi-signal selectivity of radio receivers.

The closest in technical essence to the present invention is a device for automatically adjusting the sensitivity of the receiver, which contains two independent signal amplification paths.

However, the accuracy of the adjustment is limited by the accuracy of maintaining the equality of the gain factors of the paths.

The purpose of the invention is to improve the accuracy of sensitivity adjustment.

The goal is achieved by the fact that in the device for automatic adjustment of the sensitivity of the receiver, containing an adjustable attenuator,

a serial clock generator, a time selector, a counter and a decoder, the output of which is connected to the control input of an adjustable attenuator, a series-connected comparison element, Schmidt trigger, the first inverter, the first match element and the OR element whose output is connected to another input of the time selector, D - the trigger, the D-output, the clock input and the output of which are connected respectively to the output of the Schmidt trigger, the output of the time selector and to another input of the first coincidence element, the second inverto Having an input coupled to an output latch L, second and third elements matcher, first, second and third inputs being connected respectively to the output of the first inverter, with the output of the second inverter and the first input of the controlled attenyuatoVI

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pa, the delay element, the input and output of which are connected respectively to the output of the third match element and the fourth input of the second match element, connected in series with a linear path and an amplitude detector, are additionally introduced a passband modulator connected between the second input of the adjustable attenuator and the input of the linear path, connected in series the first key and the first low pass filter, connected in series the second key and the second low pass filter, with the inputs of the first and second k The keys are connected to each other and to the output of the amplitude detector, and the outputs of the first and second low-pass filters are connected respectively to the first and second inputs of the reference element, connected in series to a pulse generator, the output of which is connected to the control inputs of the passband modulator and the second key, and the third an inverter whose output is connected to the control input of the first key.

The introduction of new blocks allows automatic adjustment of sensitivity with only one gain path, i.e. eliminates adjustment error due to nonidentity of path gains.

Nafig 1 shows a functional diagram of an automatic sensitivity adjustment device; in fig. 2 shows the dependence of the control voltage on the level of the blocking interference.

The device for automatic sensitivity adjustment of the receiver (Fig. 1) contains an adjustable attenuator 1, a passband modulator 2, a linear path 3, an amplitude detector 4, a reference element 5, a pulse generator 6, the first 7 and second 8 keys, a clock pulse generator 9, time selector 10, counter 11, decoder 12, Schmidt trigger 13, first 14 and second 15 inverters, first 16, second 18 and third 17 match elements, D-flip-flop 19, delay element 20, OR 21 element, third inverter 22, first 23 and second 24 low pass filters.

The device works as follows.

In the absence of blocking interference, the signal passes through the attenuator 1, the passband modulator 2, and after amplification in the linear path 3 is detected by the amplitude detector 4. In the presence of out-of-band blocking interference, the degree of blocking of the linear path 3 depends

from the bandwidth of the modulator 2. The bandwidth of the modulator varies periodically according to the signals of the generator 6 pulses, so the degree of blocking

also periodically changes, as a result of which the voltage of the signal at the output of the amplitude detector 4 periodically changes. The signal from the output of detector 4 is fed to the inputs of switches 7 and 8, which

0 is controlled by pulses from generator 6. Since the signal from generator 6 is fed to the control input of the key 7 through the inverter 22, the key 8 opens with a positive, and the key 7 with a negative

5 generator pulse 6. Accordingly, with a positive generator pulse 6, the bandwidth of the modulator 2 will be wide, and with a negative pulse - narrow, therefore, in the presence of blocking, the amplitude

0 signals at the outputs of the keys 7 and 8 are different. The lowpass filters 23 and 24 separate the voltages proportional to the constant components of these signals. At the same time, the frequency of the pulses of the generator 6 (respectively, the cut-off frequency of the filters 23 and 24) is chosen to be significantly lower than the minimum frequency in the spectrum of the modulating signal. Therefore, the change in signal amplitude due to the useful

0, the modulation will not affect the output levels of the filters 23 and 24. The output signals of the filters 23 and 24 are compared by comparison element 5. As a result of the comparison, element 5 forms a control voltage, which depends on the level of blocking interference. This dependence is shown in FIG. 2. The control voltage from the output of element 5 is fed to the input of the Schmidt trigger 13. When exceeding

0, the voltage from the output of the Unop level 5 element corresponding to the voltage Ui value of the noise at the input of the linear path 3, the trigger 13 is set to state 1. From the output of the trigger 13 1 is transmitted to

The 5 inputs of the inverter 14 and the trigger 19. The logical symbol at the output of the trigger 19 always lags behind the symbol at the output of the trigger 13 by one step of the operation of the counter 11. The counter 11 and the trigger 19 are clocked by the generator

0 9, formed by the inverter 14 O is transmitted to the inputs of the elements 16, 17 and 18. In this case, in any state of the trigger 19, the specified elements are set to the state O, which through the OR element

5, 21 is transmitted to the control input of the temporary selector 10. At this point, the selector 10 passes a pulse of the generator 9 to the input of the counter 11 and to the control input of the trigger 19, causing them to trigger. The impulse from the output of the counter 11 through the decoder 12 is fed to the control input control, my attenuator 1, reducing its transmission coefficient (KP) by one step. As the attenuator 1 decreases, the level of interference at the input of the linear path 3 decreases, and the magnitude of the control voltage at the output of the reference element 5 changes. If the state of the flip-flop 13 does not change, then O is again transmitted to the control input of the selector 10, the counter 11 is triggered, and the reduction in the CI of the adjustable attenuator 1 occurs by one more step. At the same time, the level of noise at the input of the linear path 3 decreases. After several cycles of the generator 9, when the voltage of the noise at the input of the linear path 3 becomes less than Ui, i.e. the voltage at the output of the element 5 is less than Ipor. (Fig 2), the trigger 13 is set and the state O is infused, while the output of the trigger 19 is 1. In this case, the output of the inverter 15 1 goes to the first inputs of the elements 16, 17 and 18. To the second input of the element 16, 1 is output from the trigger 19 output. From the output of the element 16 1, through the OR 21 element enters the control input of the time selector 10, which does not pass a generator pulse 9 to the input of the counter 11. At the same time, the control gear is fixed Attenuator 1. When the values of disturbance voltages at the input of the path 3, the control voltage on the output element 5 smaller Unop (Figure 2). Triggers 13 and 19 are set to state O. In this case, 1 from the output of the inverter 14 goes to the first inputs of elements 16,17 and 18. To the second input of element 16, O is fed, and to the second inputs of elements 1 / and 18 from the output of the inverter 15 enters 1. At the additional output of the adjustable attenuator 1, 1 is formed at maximum KP and O in all other conditions. When O comes to the third inputs of the elements 17 and 18, they are set to the state O, which is transmitted to the control input of the temporary selector 10, the time selector 10 passes the generator 9 pulse through the counter 11 to the decoder 12 and to the control input of the attenuator 1, as a result what is the reduction of its gearbox by one degree. If the state of the flip-flop 13 remains, a further reduction of the variable-voltage regulator of the attenuator 1 is continued. At values of several generator cycles 9, the flip-flop 13 is switched to the 1 state, while O is maintained at the trigger output 19. At the polarity values of the adjustable attenuator 1, it decreases to the minimum value without the state of the trigger 13 changes. The next pulse of the generator 9 puts the adjustable attenuator 1 in the state of maximum gearbox. At this moment, the third inputs of elements 17 and 18 enter 1. At the output of element 17,

1, which is transmitted to the input of delay element 20. The output logic function of the delay element 20 is delayed relative to the input logic function for the period of the complete inversion of the counter 11. So

0 as at the control input of the time selector 10 is again formed O, then the pulse from the generator 9 through the time selector 10 goes to the counter 11, which again reduces the efficiency of the adjustable attenuator 1

5 one step. After a period of complete reversal of the counter 11, when the KP of the adjustable attenuator 1 again becomes maximum and 1 goes to the third inputs of the elements 17 and 18, to the fourth input

The 0 element 18 from the output of the delay element 20 also enters 1. In the element 18, 1 is formed, which is transmitted to the control input of the time selector 10. At the same time, the control of the adjustable attenuator 1 occurs.

Claims (1)

The claims of the device Automatic sensitivity adjustment receiver, containing an adjustable attenuator, 0 connected in series clock generator, time selector, counter and decoder, the output of which is connected to the control input of an adjustable attenuator, connected 5 in series comparison element, Schmidt trigger, first inverter, first match element and OR element whose output is connected to another time selector input, D-flip-flop, D-input, clock 0 the input and output of which are connected respectively to the output of the Schmidt trigger, to the output of the time selector and to the other input of the first coincidence element, the second inverter whose input is connected to the output of the D-flip-flop, the second and third matching elements, the first, second and third inputs connected respectively to the output of the first inverter, to the output of the second inverter and to the first output 0 adjustable attenuator, a delay element whose input and output are connected respectively to the output of the third match element and to the fourth input of the second match element, connected by a sequentially linear path and amplitude detector, characterized in that, in order to increase the sensitivity adjustment accuracy, bandwidth modulator connected between second output adjustable an attenuator and a linear path input connected in series with the first key and the first low-pass filter, with the inputs of the first and second keys connected to each other and with the output of the amplitude detector, and the outputs of the first and second low-pass filters are connected respectively to the first and the second inputs of the comparison element, connected in series by a pulse generator, the output of which is connected to the control inputs of the passband modulator and the second key, and a third inverter, the output of which is connected to the control input of the pey key. G / RB-G # -1/2 K / 71 Qp Fig 1 ISrZHZHKrL- t ,, f P - EPL-I and, P