SU1166332A1 - Clocking device - Google Patents

Abstract

A TACT SYNCHRONIZATION DEVICE containing an in-phase channel consisting of a first integrator connected in series, a first limiter and a sign detection detector, and an average phase channel consisting of a second integrator connected in series, a second limiter and a first delay element, and the output of the sign of the in-phase channel detecting signal and the output of the first delay element of the middle-phase channel through a series-connected multiplier and reversible counter is connected to the control input The generator, the outputs of which are connected respectively to the reset inputs of the first phase channel integrator and the second middle phase channel integrator, the signal inputs of which are combined and are the device input, characterized in that, in order to increase the synchronization accuracy for a given synchronization time, it is entered an additional limiter connected in series, a second delay element, a mismatch element, a lower filter and a threshold block, with the additional limiter input is combined with CO of the first integrator input signal phase channel, the output of the first limiter-phase channel is connected to another input of element mismatch, and a threshold unit output is connected to the control input of the reversible counter. a: One with so

Description

The invention relates to telecommunications, namely digital telephony, and can be used in digital information transmission systems.

The purpose of the invention is to improve the synchronization accuracy for a given time to join synchronism.

FIG. Figure 1 shows the electrical circuit diagram of the synchronization device; in fig. 2 - timing diagrams for the operation of the device.

The clock synchronization device contains the first integrator 1 of the in-phase channel, the second integrator 2 of the middle-phase channel, the first and second limiters 3 and 4, the sign detection detector 5, the first delay element 6, the multiplier 7, the reversible counter 8, the controlled oscillator 9, the additional limiter 10, the second delay element 11, the mismatch element 12, the low-pass filter 13 and the threshold unit 14.

The clock synchronization device operates as follows.

The mixture of signal and noise (Fig. 2a) is fed to the first input of the integrators 1 and 2 of the common-mode and middle-phase channels and an additional limiter 10. From the outputs of the integrators 1 and 2, the accumulated signal (Fig. 26 and 2b) goes to the inputs of the first and second stops 3 and 4, in which the voltage sign at the output of integrator 1 and 2 is highlighted at the time of arrival of the integrator reset pulses for integrator 1 (Fig. 2a). At the output of the second delay element 11, the amplitude-limited signal from the output of the preselector is equalized in time (Fig. 2e) with the signal at the output of the first limiter 3.

Thus, on the mismatch element 12, a signal allocated by the device of clock synchronization and a limited source signal appear. The mismatch in time of these two sequences characterizes the tracking error. While the synchronization loop is open, it is obvious that the mismatch time is 0.5 of the time.

observation. On the mismatch element 12, pulses of the same amplitude and duration corresponding to the mismatch time are generated (Fig. 2e). The signal from the output of the mismatch element 12 is smoothed in the low-pass filter 13 (Fig. 2g). The voltage at its output is proportional to the timing error. The threshold in threshold block 14 is set according to calculations. After triggering threshold block 14, i.e. when the synchronization error becomes less than the specified threshold, the threshold is triggered (Fig. 2g), the output of the threshold unit 14 is a control signal, which switches the counting factor of the reversible counter 8 from small to larger, which corresponds to the narrowing of the bandwidth of the clock synchronization device.

The bandwidth of the system with astatism of the 1st order of uf, where K is

open loop gain. In turn, K discriminator, K controlled generator, K rev. counter. Thus, the gain factor of the reversible counter. linear

associated with the gain and bandwidth of the clock synchronization device, and hence the switching of the counting coefficients leads to a change in the timing of the occurrence in the synchronization.

The proposed clock synchronization device allows a reduction in the time taken to synchronize. It corresponds to the time it takes to synchronize a high-band clock synchronization device. At the same time, the error

tracking in synchronization mode is small, since after establishing the fact of signal capture, the bandwidth is automatically reduced by switching the counting factor of the reversible counter. The newly introduced blocks 10–14 serve to establish the fact of synchronization over a wide band and automatically switch lanes after a fast capture.

 tx 1

-four

Xlx

-I 1

PP

A

3

J l

/////////////////////////////////

FIG. 2

Claims (1)

A TACT SYNCHRONIZATION DEVICE comprising a common mode channel consisting of a first integrator, a first limiter and a sign detection detector connected in series, and a medium phase channel consisting of a second integrator, a second limiter and a first delay element connected in series, the output of the common mode channel sign detection detector and the output of the first delay element of the medium-phase channel through a series-connected multiplier and a reverse counter are connected to the input of the controlled gene an amplifier whose outputs are connected respectively to the reset inputs of the first integrator of the common-mode channel and the second integrator of the middle-phase channel, the signal inputs of which are combined and are the input of the device, characterized in that, in order to increase the accuracy of synchronization at a given time of entering into synchronism, series-connected an additional limiter, a second delay element, a mismatch element, a low-pass filter and a threshold block, while the input of the additional limiter is combined with gnalnym input of the first integrator I-channel, I-channel output of the first limiter is connected to the other input element mismatch, and a threshold unit output is connected to the control input of the reversible counter. <Rig. 1>