RU1807568C - Device for detection of symmetrical signals - Google Patents

Abstract

The inventive device includes 3 delay lines 1, 2 and 11, 2 switches 3 and 4, 1 multiplier 5, 1 integrator 6.1 memory unit 7, 1 sampling unit 8, 1 clock generator 9, 1 counter 10, 2 ill.

Description

The invention relates to radio and communications technology and can be used to detect time-symmetric signals (even or odd) against a background of interference. Even and odd signals are most often found in radio engineering and other areas of technology:

The aim of the present invention is to increase the signal-to-noise ratio and thereby increase the reliability of detection of symmetrical signals against a background of interference.

In FIG. 1 is a block diagram of a device for detecting balanced signals; in FIG. 2 is a plot of the ratio of the noise power at the output of the device to the squared noise power at the input versus the product of the noise band and the signal duration.

The device for detecting symmetrical signals contains the first 1 and second 2 delay lines with taps, the first 3 and second 4 switches, a multiplier 5, an integrator 6, a memory unit 7, a sampling unit 8, a clock generator 9, a counter 10 and a third delay line 11. The input of the device is the combined information inputs of the first 1 and second 2 delay lines. The output of the device is the output of the sampler 8. The inputs of the first 1 and second 2 delay lines receive an input signal, discretized in time. The clock generator 9 generates clock pulses that are not received by the input of the counter 10. The conversion factor N of the counter 10 is equal to the number of taps of the first 1 and second 2 delay lines. The first counter output is connected to the clock inputs of the first 3 and second 4 switches.

Pulses are generated at the second output of counter 10. Corresponding to each Nth input pulse. The pulses from the second output of the Counter 10 are used to record information coming from the output of the integrator in the memory unit 7. The pulses delayed in the delay line 11 serve to reset the integrator 6 to the zero state.

A delay in line 11 is necessary to prevent loss of information at the time of the reset of the integrator 6. The delay should be at least a period of clock pulses. Impulses from output Li00 O

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O1

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00

delay lines 11 serve to shift the input information in the first 1 and second 2 delay lines. During the time between the pulses arriving at the clock inputs of the delay lines 1 and 2, all the taps of the delay lines are interrogated by switches 3 and 4.

Thus, the inputs of the multiplier receive information from all outputs of the delay lines 1 and 2, and, thanks to the fact that the first 3 switch is connected to the inputs of the first 1 delay line in the direct order, and the second 4 switch is connected to the inputs of the second 2 delay limit in the reverse order, at the output of the integrator b, a signal is generated that is similar to the convolution in the finite limits:

Sn (l, k) (1 / N) | SiO-k) Si (l-N-fk), (1)

where Si is the input signal;

Sn-signal at the output is overloaded;

G is the reference number of the input signal; k O ... N is the sum index determined by the address of switches 3 and 4, arriving at the 5th count (and 10,:

H is the number of samples stored in lines for Arrows 1 and 2.

The integrator; -, 6 calculates the average value of the product of input samples at index k. The final value of the sum at the output of the integrator 10 is stored in the memory unit 7. The sampling unit 8 serves to determine the moment: the signal reaches its maximum and stores this value.

If the time of occurrence of the signal is known, then a storage fetching device can be used as block 8. There is no time for the appearance of the signal, yr, then as a block 8, I can use a threshold device. In this case, the threshold is set, proceeding from the required statistical parameters, it is found: NYA.:; -: -L: .- - --L. ::.,:,.,.; :: - ,.:, H, -,: ..:; /:

The detection device may be implemented on the elements of digital or combined analog-digital technology. Conversion factor N counter 10

and the frequency ft of the clock 9 is determined from the following relationships:

N Tc / tg, (2) tg N / ft 1 / 2fo, (3)

where Tc is the signal duration;

tg-signal sampling time; f0 is the maximum frequency of the signal spectrum. Choosing tg from condition (3).

relation (2) and we find ft - N / Tc, for example fо 1 kHz, Tc 1 ms, then tg 0.5 ms. We take tg 0.1 ms, hence N 10, ft 50 kHz. The use of additional nodes and the connections between them distinguishes the proposed device for detecting symmetrical signals from the prototype device, because In order to improve the signal-to-noise ratio, it means improving the reliability of signal detection.

Formula of the invention

A device for detecting symmetrical signals, comprising a sampling unit, a multiplier, the output of which is with the first input of the integrator, from. In addition, in order to increase the reliability of detecting symmetrical signals, three delay lines, two switches, a memory unit, a counter and a clock generator are introduced, the output of which is connected to the counter input, the first output of which is connected to the clock inputs the first and second switches, the outputs of which are connected respectively to the first and second inputs of the multiplier,

the second counter output is connected to the clock input of the memory unit and to the input of the third delay line, the output of which is connected to the clock input of the integrator and to the clock inputs of the first and second lines

delays, the outputs of which are connected to the information inputs of the first and second switches, the integrator output is connected to the information input of the module, the output of which is connected to the input of the sampling unit, the output of which is the output of the device, the input of which is the combined information inputs of the first and second delay lines.

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Editor

FIG 2

Compiled by T. Zamorova Tehred M. Morgenthal

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Proofreader L. Pilipenko