SU1594694A1 - Pulse duration to code converter - Google Patents

Abstract

The invention relates to an information-measuring technique and can be used in converters of time-frequency parameters of pulse signals into a code. The purpose of the invention is to improve the noise immunity. To do this, the device containing elements 2 and 3 OR-NOT, counter 4, RS - flip-flop 5, entered D-flip-flop 1. Introduction of D-flip-flop and changing the corresponding connections allows for the selection of pulses in duration, thereby distinguishing the interference and useful signal. In addition, the device allows the frequency to be converted to code also with frequency selection. 1 il.

Description

 The invention relates to information measuring equipment and can be used in frequency-time parameters converters.

pulse signals in the code.

The purpose of the invention is to improve the noise immunity.

The drawing shows the functional diagram of the Converter.

The igg- - pulses-to-code duration converter contains a P-flip-flop, an OR-NOT 2 and 3 element, a counter 4, an RS-flip-flop 5, a clock bar 6, an input bus 7, a bus 8 initial set, an output 9 and a signal 10 w; .-ny.

Converter works as follows

The impulse received through bus 8 sets the device: o to the initial state and translates into the measurement standby mode, while the outputs of the triggers 5 and 1 have a zero level, clock pulses, fasting-1D through the bus 6, pass through

an open element ШИИИ HEi 2 on the clock input of the counter 4, which, however, does not change its state due to the presence of a unit of potential at zero at the input if there is no pulse on the input gain 7,

When a pulse arrives on the bus 7 at the output of the OR-NOT 3 element, a zero-counting signal appears. During the pulse operation on the bus 7, the counter 4 counts the number of clock pulses transmitted to its clock input. The useful signal and interference in this case differ in the duration Dp of this. One of the bits of counter 4 (output 1) is used, which is selected from the condition

(2 -,) I, t ,,, -

where i is the bit number of the counter;

T - the period of clock pulses;

t - maximum duration t-. interference,

If a useful signal is received on bus 7, and not a disturbance, then counter 4 is at least once before d. sinks to i-ro bit, as a result of which a +1 level appears at the output of +1 of the counter 4, which sets the trigger 5 to the 1 stage, which in turn

Enables operation of trigger 1 on a clock input. At the moment of the end of a pulse on bus 7, trigger 1 is set to one, the blocking element OR NOT 2, and the clock pulses no longer arrive at the clock input of counter 4, After the end of the pulse on bus 7, the output of the SHS-NOT 3 element is kept zero, since the trigger 1 is in the unit state. Counter 4 stores the code corresponding to the measured pulse duration that went through the bus 7. Further receipt of the pulses through the bus 7 does not cause any changes. of the state of the counter, whereby the power of the pulses can be arbitrary and they are perceived as a disturbance. The occurrence of a unit level on bus 10 indicates the completion of the conversion, and the code generated in counter 4 can be read over bus 9. After - reading the result of the conversion, bus 8 is given a pulse and the device goes back to its original state,

If the bus 7 receives a pulse interference after the device is reset, the converter starts working as with a useful signal, but in this case, the counter 4 does not count to the 1st bit and the output +1 of the counter 4 is a single level does not appear. The trigger 5 remains in the zero state, keeping the trigger 1 also in the zero state, and at the end of the pulse on the bus 7, the counter is reset to zero, and the device is on-standby.

Thus, the device allows to suppress the interference occurring on the input bus 7, with a duration less than the one specified in the interval between the initial setup pulse and the desired signal, as well as any duration after the useful signal, the rtpH result of the conversion is not distorted.

In addition, the device allows conversion to a code and an unknown frequency. To do this, the bus 7 must be supplied with a reference interval during which the number of pulses of unknown frequency fed to the bus 6 is counted. In this case, it is possible to select the input frequencies, Tee, choose a certain bit

counter 4 as

+1

output

frequencies below certain (-l) / Tj, where T, is the duration of the reference pulse, are cut off,

Claims (1)

In case it is necessary to obtain smaller gradations for selection both in terms of pulse duration, frequency and frequency, you can use the trap element I) for a specific code, or a digital comparator, the element of comparison. Formula isob Rete n i Preset the pulse duration into a code containing the first and second elements OR NOT, the first inputs of which are the clock and input buses, respectively, the RS flip-flop, the R-input of which is the bus on and the output is connected to the second input of the second element OR NOT, the output of the first element 1 nta OR is NOT connected to the clock input of the c leT, the output of which is the output bus of the converter, characterized by the fact that A D-trigger is introduced, the clock input of which is an input bus, B-in is combined with the R-input and connected to the RS-trigger output, and the output is connected to the second input of the first element OR NOT, the output of the second element SH-NOT is connected, not with the installation input in About the counter, the i-th output of which connect ene with S-input of RS-flip-flop, where n and - a width of the counter, the output D-flip-flop is a signal line.