SU1193600A1 - Apparatus for time reference to extreme values of harmonic signal - Google Patents

Abstract

DEVICE timing to extreme values of a harmonic signal, comprising a generator, a limiting amplifier, the first, second, third and fourth keys, the control trigger member GI, an OR gate, element.zaderzhki, up counter, and the recording element down counter, the data inputs the recording element is connected to the output bits of the summing counter, and the outputs are elec. The recording records are connected to the installation inputs of the counting counter, while the generator output is connected to the first input of the first key, the output of which is connected to the counting input of the summing counter, the outputs of the second and third keys are connected respectively to the S input and the R input of the control trigger, one of the outputs of which is one of the outputs of the device and is connected simultaneously to the first input of the ZI element, the output of which is connected to the first input of the OR element whose output is connected to the counting input of the subtracting counter The input bus of the device is connected to the input of the amplifier-limiting device, characterized in that, in order to improve the accuracy of binding to extreme values of the harmonic signal and expanding the frequency range, a D-flip-flop, a decoder, a driver, a second ZI element, an input are entered into it. which is connected to the second output of the control trigger, a delay element and a summing counter, the generator output being connected to the D input of the D flip-flop, the D input of which is connected to the output of the limiter yci-shitel, the first output of the D-flip-flop connected to the first inputs of the ZI and the first key, as well as to the first input of the third key, its (L second output to the second inputs of the second ZI element and the fourth key, as well as to the first input of the second key, the second inputs of the second and third keys are connected to the output of the imaging unit and the input of the record of the subtracting counter, the output bit buses of which are connected to the corresponding input buses of the decoder, the output O5 of which is connected to the input of the imager, in addition, the outputs of the second and third keys are connected respectively to The first and second delay elements and, respectively, the first and second inputs of blocking the transmission of the code on the primary and secondary information buses of the recording element, the additional information buses of the recording element are connected to the corresponding code bits of the second summing counter, and the reset inputs of the first and second counters connected respectively to the outputs of the first and

Description

the second delay elements, the third inputs of the ZI elements are connected to the generator output, the output of the second ZI element is connected to the second input of the OR element, the output of the fourth key is connected to the counting input.

- a summing counter, and the inputs of the recording of summing meters and the reset input of the counting meter are connected to the bus. The device starts, the second output of which is the second output of the control trigger.

The invention relates to radio measurements and is intended for use in wide-range measurements of the frequency-time parameters of signals.

The purpose of the invention is to improve the accuracy of coupling to extreme harmonic signal values and to expand the frequency range of the device by eliminating the error that is caused by the asymmetry of the signal and suppressing the noise component in the signal.

The expansion of the frequency range is determined by the reduction in the speed requirements of the counter13, which is provided as a result of anchoring not only to the positive, but also to the negative half-wave of the signal.

FIG. 1 is a block diagram of the device; in fig. 2 and 3 are timing diagrams that explain its functioning.

The device contains a generator 1, the amplifier-limiter 2, the first 3, the second 4, the third 5 and the quarter 6 keys, control trigger 7, ZI 8 sensor, OR 9 element, delay element 10, summing counter 11, recording element 12 and output counter 13 The information buses of the recording element 12 are connected to the output bits of the summing counter 11, and the outputs of the recording element 12 are connected to the installation inputs of the detracting counter 13. The output of the generator 1 is connected to the first input of the first key 3, the output of which is connected to the counting input its counter 11, the outputs of the second 4 and third 5 keys respectively connected to S-input and the R-input of the control flip-flop 7, one of whose outlets is one of the outputs smiling

device connected simultaneously to the first input of the element ZI 8, the output of which is connected to the first input of the element OR 9, the output of which is connected to the counting input of the subtractive counter 13, and the input bus of the device is connected to the input of the amplifier limiter 2.

In addition, the device contains

10 D-flip-flop 4, - decoder 15, formative 16, second element, ZI 17, delay element 18 and summing counter 19 ,. moreover, the output of the generator 1 is connected to the C-input of the D-trigger 14

tS D-input of which is connected to the output of the amplifier-limiter .2, the first output of the D-flip-flop 14 is connected to the second inputs of the first ZI element of the first key 3, as well as to the first input

20 of the third key5. The second output of the D-trigger 14 is connected to the second inputs of the second element ZI 17 and the fourth. the key 6, as well as to the first input of the second key 4, the second outputs of the second 4 and third 5 keys are connected to the output of the driver 16 and the write input of the subtracting counter 13, the output bit buses of which are connected. with the corresponding input buses of the Deshi fractioner 15, the output of which is connected to the input of the imaging unit 16.

The outputs of the second 4 and third 5 keys are connected respectively to the inputs of the first 10 and second 18 delay elements and respectively to the first and second inputs of blocking the transmission of a code on the main and additional information buses of the recording element 12, the additional information buses of the recording element 12 are connected to the corresponding output bit buses of the second summing meter 19, and the reset outputs of the second 19 and first 11 summing meters are connected respectively to the outputs of the first 10 and second 18 delay elements, three The inputs of the ZI elements 8. and 9 are connected to the output of the generator 1, the output of the second element of the ZI 17 is connected to the second input of the element OR 9, the output of the fourth key 6 is connected to the counting input of the second summing counter 19. The write inputs of the summing counter 11 and 19 and the reset input of the subtractive counter 13 is connected by a bus. The device starts, the second output of which is the second output of the control trigger 7, and this output is connected to the first input of the second element ZI 17, the device works as follows. Suppose that a harmonic signal is input to the input of the device, in which there is no noise (Fig. 2c ()) Square-shaped pulses are formed at the output of the limiter amplifier (Fig. 2SC), the edges and cuts of which correspond to the transitions of the input signal through the zero level. The D input of the D flip-flop 14, to the C-input of which pulses are sent from the output of generator 1. The clock frequency f from the output of generator 1 (Fig. 2c) significantly exceeds the frequency of the input signal F. D-flip-flop 14 switches over the rear front of bars x pulses. As a result, at its output a signal is formed, shown in Fig. 2 -. We suppose that at the moment of the device start-up the counters 11, 13 and 19 are in an arbitrary state (Fig. 23, e i Y). In addition, the control trigger 7 is in the unit state (Fig. 2k-), and the clock pulses through the open first key 3 to the counting input of the first summing counter 11, whose code increases linearly with time (Fig. 2i). At the same time, the clock pulses through the ZI element 8 and the OR element 9 are passed to the counting input of the subtracting counter 13, the code which decreases linearly with time (Fig. 2; s). If during the time of the positive half-wave of the input signal the code of the subtracting counter does not reach zero, then during the negative half-wave of this signal all the counters will remain unchanged, and with the arrival of the next positive half-wave of the input signal, the code 11 will increase and the code will decrease by counter 13. At the moment when the counter 13 reaches a zero code value, a short pulse is formed at the output of shaper 16 (Fig. 25-). By this impulse, through the open third key 5, the control trigger is transferred to the zero state (Fig. 2i). As a result, the element ZI 8 closes, which stops the arrival of clock pulses at the counting input of the detracting counter 13. In addition, the pulse from the output of the shaper 16 is fed to the recording input of the deducting counter 13 and the third key 5 to the second input of the transmission block of the entry element 12, which leads to the unblocking of the transmission of the code from the second summing counter 19 via additional information buses to the recording element 12. The latter transmits the code received from counter 19 to the installation inputs of the subtracting counter by halving this code, and the doubled code value of counter 19 is entered into the subtracting counter 13, since the impulse from the output of transformer 16 is present at its recording input. sufficient for presetting the subtracting counter 13 and the time delay 18 set by the element 18, the summing counter is reset to the zero state. Until the end of the current positive half-wave of the input signal, the state of the counters 16 and 19 will not change. The next negative half wave closes the first key 3, i.e. the flow of pulses to the counting input of the counter 11 is stopped; at the same time, the fourth key 6 and the ZI element 17 are opened so that the clock pulses begin to arrive at the counting inputs of counters 13 and 19. If during the negative half-wave action of the input signal, the counter 13 reaches zero code value, then, just as in the previous case, the output of the driver 16 will generate a pulse that will switch the control trigger 7 to one (Fig. 2 will write to the subtracting counter 13 of the halved code of summing counter 11 and reset the last. During the negative The first half-wave in the summing counter 19 will be fixed with the code K ff, the value of which is proportional to the duration of this half-wave I. The duration C of the next positive half-wave will correspond to the code on the counter 11 M. The sum of the N + M codes corresponds to the period T of the input signal. N. is alternately (but halved) written to subtractive counter 13. This recording is made when the passing counter reaches zero status. In this case, the subtracting counter performs the functions of a code-interval transducer r time: its zero-crossing times correspond to the midpoints of the positive and negative half-waves of the input signal. These average moments are determined based on the durations of the respective half-waves of the input signal in the previous period. Do not learn the delays introduced by the limiting amplifier 2, it is easy to see that these moments of time correspond to the extreme values of the input signal, which. these moments do not depend on the drift of the zero line of the limiting amplifier, i.e. asymmetry restrictions. As output signals of the device, either rectangular pulses from the outputs of the control trigger 7 or the coupling pulses at the output of the second 4 and third 5 keys can be used. In this case, the coupling to both extreme values of the signal is provided and this is done with the same accuracy, which is due to the quantization error (determined by the clock frequency) and the delay of the amplifier of the limiter 2. The duration of the transient TV device depends on the initial values of the codes on the counters and the frequency of the input signal. signal. This duration can be reduced to one period of the input signal if the meters are preset to a state that corresponds to about a quarter of the period of the highest frequency signal. Technical difficulties such preset does not cause. The device does not have strict time requirements for summing counters, since the code is overwritten from the summing counter into the subtractive counter in statics when the counting pulses do not arrive at the counter input of this counter. The required volume of counters (their width) is determined by the lower operating frequency and the frequency of clock pulses. As a result, the limitation on the lower operating frequency of the device is removed, which expands its operating range. Under the conditions of exposure to noise with a wide frequency band, the device operates as follows. Let the input signal be as shown in FIG. 3 ", the device counters accordingly. preset, and the control trigger 7 is in a single state. At the output of the limit amplifier 2, a signal is formed as shown in FIG. 35. During the stay of the mixture of signal and noise above the zero level (this corresponds to the single state of the D-flip-flop 14) the code of the summing counter 11 increases in proportion to the integral duration of the formed signal (at the output of the D-flip-flop) above zero, and the code of the deducting counter 13 decreases and at some point reaches zero. At this moment, as with working with a clean (no noise) signal, the reduced counter code 19 is entered into the subtracting counter, the control trigger 7 is switched, the summation counter begins to accumulate a code corresponding to the integral time of the signal mixture and noise below zero. The code of the subtracting counter 13 decreases, reaching zero in the same half-period of the input signal (Fig. 33). At this moment, the reduced counter code 11, corresponding to the integral

pulse duration on the considered time interval. If at subsequent time intervals within a given signal period the integral pulses and pauses (at the amplifier output) exceed their halved values that were accumulated during the previous observation interval, then the device will experience multiple false positives in the transient process, which will increase its duration. However, the codes of the summing counters will gradually change, rushing to values that are proportional to the average over the period of the signal's residence time above (below) the zero level. Moreover, the most probable moments when the output code of the subtracting counter 13 reaches the zero state are the moments of the transition of the input signal through extreme values, which are least subject to the effects of noise. As a result, the output of the device (Fig. ZZ) is established, the sequence of rectangular pulses, the frequency of which corresponds to the frequency of the input signal, and the fronts of the pulses - to its extreme values.

The error of reference in this case is determined by the statistical properties of the integral pulse duration (pauses) at the output. Limiting amplifier 2. The same factor is also responsible for the noise immunity of the device. False alarms occur if the integral pulse duration (pauses)

in the previous period, the signal is more or less than twice its value in a given signal period. However, if we take into account that the spread of the integral estimates of the pulse durations (pauses) is much less than the instantaneous values, which is due to the averaging effect, then the failure resistance of the proposed device is quite high.

In addition, the binding of the pulse fronts, which are formed at the output of the D-flip-flop, makes the device

low-critical to changes in the element delays, eliminates the fragmentation of counting pulses due to noise, which allows maximum realization of its capabilities from the point of view of noise immunity to broadband noise.

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Claims (1)

DEVICE FOR TEMPORARY LINKING TO EXTREME HARMONIC SIGNAL VALUES, containing a generator, limiter amplifier, first, second, third and fourth keys, a control trigger, a ZI element, an OR element, a delay element, a totalizing counter, a recording element and a subtracting counter, and the information inputs of the element records are connected to the output bit 'buses of the totalizing counter, and the outputs of the recording element are connected to the installation inputs of the subtracting counter, while the output of the generator is connected to the first input, the first key the output of which is connected to the counting input of the totalizing counter, the outputs of the second and third keys are connected respectively to the S-input and R-input of the control trigger, one of the outputs of which is one of the outputs of the device and is connected simultaneously to the first input of the ZI element, the output of which connected to the first input of the OR element, the output of which is connected to the counting input of the subtracting counter, and the input bus of the device is connected to the input of the amplifier-limiter, characterized in that, in order to increase the accuracy of binding to the extreme values of the harmonic signal and the expansion of the frequency range, a D-flip-flop, a decoder, a shaper, a second ZI element, the input of which is connected to the second output of the control trigger, a delay element and a totalizing counter, are introduced into it, and the generator output is connected to the C-input of the D-flip-flop , The D-input of which is connected to the output of the amplifier of the limiter, the first output of the D-trigger is connected to the second inputs of the first ZI element and the first key, as well as § to the first input of the third key, its second output to the second inputs of the second ZI element and h of the fourth key, as well as to the first input of the second key, the second inputs of the second and third keys are connected to the output of the shaper and the write input of the subtracting counter, the output bit buses of which are ⁴ connected to the corresponding input buses of the decoder, the output of which is connected to the input of the shaper, except Moreover, the outputs of the second and third keys are connected respectively to the inputs of the first and second delay elements and, respectively, to the first and second inputs of blocking the transmission of code by the main and additional information buses of the recording element, and additional information buses of the recording element are connected to the corresponding output bit lines of the second totalizing counter, and the reset inputs of the first and second counters are connected respectively to the outputs of the first and SU .1193600 of the second <delay element, the third inputs of the elements * 'are connected to the output of the generator, the output of the second element is connected to the second input of the OR element, the output of the fourth key is connected to the counting input of the second 1193600 totalizing counter, and the recording inputs of the summing counters and the reset input of the subtracting counter is connected to the Start bus of the device, the second output of which is the second output of the control trigger.