SU1265982A1 - Pulse burst -to- rectangular pulse converter - Google Patents

Abstract

The invention relates to a pulse technique. It can be used in automation and telematics devices to convert a burst of pulses into one rectangular, pulse. The purpose of the invention is to improve the robustness of the converter to skip the input pulses. To do this, the device containing the triggers 27, 7, 15, reversible counters Mib 12, 14, element OR - NO 25, elements AND 4, 5 generator 24 reference pulses, input I, first 6 and second 20 output 1iiny and bus “Reset 10, entered elements OR 9, 11, 13, elements AND 21, 22, 26, triggers 16, 19, reversible counters 17, 18, prohibition element 8, waiting for multivibrator 2, delay element 3, third output IHI 23 The goal is achieved by introducing a delay in the formation of the leading and trailing edges of the pulse at the third output, which is provided by counters 17, 18. And the measurement of the intervals between pulses and the recovery of the missed pulses produce two reversible counters, alternately counting the reference pulses in the c, identity and subtraction modes. The presence in the converter of three outputs with 5 different combinations of two ocHoii properties: noise immunity and speed allows to expand the area of its application. 2 Il. al GO Ot) ate with 00 1chE liZff

Description

The invention relates to a pulse technique and can be used in pulse signal processing devices.

The purpose of the invention is to increase noise immunity to missing input pulses. ⁵

In FIG. 1 shows a functional electrical diagram of a device; in FIG. 2 - time diagrams of his work.

The converter of the pulse train into a rectangular pulse contains an input bus ίο I connected to the input of the standby multivibrator 2, with the input of the delay element 3, with the first input of the first element And 4 and with the input of the first trigger, the direct output of which is connected to the second input of the first element And 4 and the first input of the second aND gate 15 is 5, the inverse output - to the first output line 6, the first adjusting input - a first adjusting input of the second flip-flop 7, the output member 8 of prohibition and the first input of the first elements that θ ₂ OR 9, in the second installation One is connected to the second installation input of the trigger 7, the input bus 10 "Reset" and the first input of the second element OR 11, the second input of which is connected to the output of the first counter 12, and the output to the first 25 input of the third element OR 13, the installation input of the second counter 14 , the installation input of the third trigger 15, / 7-input of the fourth trigger 16, the installation inputs of the third 17 and fourth 18 counters and / 7-input of the fifth trigger 19, 30 whose inverse output is connected to the second output bus 20, and the S-input - with the output third element AND 21, the first input which is connected to the output of the counter 14, and the second input to the first input of the fourth element And 22 and direct output 35 of the trigger 7, the inverse output of which is connected to the third output bus 23, and the counting input to the output of the element And 4, the output of the generator 24 reference pulses connected to the second input of the And 22 element and the second input of the And 5 element, the output of which is connected to the counting inputs of the counters 12 and 14 and the counting input of the counter 18, the control input of which is connected to the direct output of the trigger 15, and the output to the first input of the element OR — NOT 25, 45 second entrance of koto the second one is connected to the output of the counter 17, and the output is connected to the first input of the fifth AND 26 element and the first input of the inhibit element 8, the inhibitory input of which is connected to the output of the standby multivibrator 2 and the second input of the And 50 element, and the second input to the direct output of the trigger 16 , S-input of which is connected to the output of aND 26, adjusting an input 12 connected to the counter output of the OR gate 13, a second input coupled to an output of the delay element 3 and a second building element ⁵⁵ vho- OR 9, the output of which is connected to the counting input of the flip-flop 15 , inverse output which is connected to a control input of the counter 17, the count input coupled to an output AND gate 22.

Counters 17 and 18 are reversible, triggers 27, 7, 15, 16, 19 can be performed on 133TV1 microcircuits.

The device operates as follows.

The elements are set to their initial state by applying a reset pulse to the input bus 10. The initial state of the triggers 27, 7, 15, 16, 19 is “0”, the counters 12 and 14 are all “0”. The direct code proportional to [Δ7 / 2] is written to the counters 17 and 18 in the initial state, where Δ7 is the pulse duration of the waiting multivibrator 2 (Fig. 26). The duration of the overflow pulses is equal to the duration of the pulse reference pulses. Triggers 27, 7, 15, 16 and 19 switch on the trailing edges of the pulses at the unit and counting inputs. The reversible counters 17 and 18 operate in the addition mode if the control input has a high level potential, and in the subtraction mode if the potential is low at the control input.

Reverse counter modules 17 and 18 are determined by the formula where I is the maximum number of consecutively missed pulses;

Gchake - the largest period of the sequence of input pulses;

/ o = -] ------ period of the reference pulses.

The time intervals between bursts of pulses must satisfy the inequality: T _n > (l + V) -T.:, _Ki ,

A pack of n pulses, the repetition period of which can vary from pack to pack within (Гм _И1! - Тч ·. ^), Enters the conversion bus 1 (Fig. 2a). At the output of the waiting multivibrator 2, a packet of strobe pulses is formed (Fig. 26), of duration Δ7, determined by the given instability of the period 67

Δ7 = 67 · 7max.

The first pulse of the packet trailing edge switches to "1" trigger 27 (Fig. 2i), which allows the receipt of reference pulses to the inputs of the counters 12 and 14, counting time intervals 7 ₃ , and to the input of the reversing counter 18, operating in the subtraction mode. After a time Δ7 / 2, the delay element 3 generates a first delayed pulse (Fig. 2B), switching the trigger 15 to "1" (Fig. 26). At this moment, the code “00 ... 01” is stored in counter 18 and it starts to count reference pulses in the addition mode, measuring the interval T1 between the first and second pulses of the packet. By the time the second delayed pulse arrives, the counter 18 counts the pulses

The second pulse of the packet switches the trigger 7 to “I” (Fig. 2k), which allows the receipt of reference pulses to the counting input of the reverse counter 17. At the time of switching the trigger 15 to “O”, the code “00 ... 01” is stored in the counter 17 and he begins to measure the interval T2 between the second and third burst pulses. With the equality of K1 = K2, T1 = T2 there is an overflow of the counter 18, operating in the subtraction mode. An overflow pulse is generated when the counter reaches the state “00 ... 0” at the moment of receipt of the third pulse (Fig. 2e). In this case, an impulse is formed at the output of the And 26 element, switching the trigger 16 to “1”. Measurement and comparison of two successive intervals with the help of reversible counters 17 and 18 is necessary for reliable determination of the repetition period in the conditions of loss of input pulses.

In the case of missing burst pulses, the intervals Τ ,, T2 are unequal, therefore, an overflow pulse is not formed (at Ti> T ₂ ) or is formed, but does not coincide with the third strobe pulse (at T | <T2). Then, switching trigger 16 to “1” occurs when two any consecutive intervals 7 are equal, _i = 7 _f . The measured value of the repetition period is necessary for the subsequent restoration of the missed pulses of the packet.

The trigger 16 allows the recovery of missed pulses of the burst produced by element 8 "Prohibition". It passes overflow pulses while skipping input pulses and, accordingly, strobe pulses (Fig. 2e). If I pulses are skipped in succession, the counters 17 and 18 generate I overflow pulses, which, at intervals of T, go to the counting input of trigger 15. The first pulse of the burst again synchronizes trigger 15 relative to the burst pulses. The restored burst pulses are reset to “0” of the trigger 27 and 7, forming pulses on the output buses 6 and 23.

The delay time T3, relative to the first pulse of the packet, is counted in the counter 14, which counts the reference pulses. The delay time is determined by the expression 73] 7> (/ - | - 1) · 7max = M | · / О, where АЦ - counter module 14.

The counter overflow pulse 14 (Fig. 2h) switches trigger 19 to “1” if the burst consists of several pulses (n ^ 2) (Fig. 2l). If a single interference impulse arrives, the overflow impulse is not passed by the And 21 element, since the trigger 7 remains in the “0” state, and the formation of the leading edge of the impulse on the output bus 20 does not occur.

The formation of the trailing edge of the pulse on the output bus 20 is performed by the trigger 19 for the counter overflow pulse 12 after a time T ₃₂ relative to the last pulse of the burst, resetting the counter to "0". For the three-dimensional conversion of bursts of pulses of duration T _{about, the} modules of the counters 14 and 12 are chosen equal to Μι = Μ ₂ , which ensures equal delay times ^ 31 = 732, then 7o = 7out ₂ and the formation of pulses on the output bus 20 is more noise-resistant than on the output buses 16 and 23, since the introduction of a delay in the formation of both edges of the pulse at the output of the trigger 19 provides high noise immunity to missing input pulses, both single and group (Fig. 2L).

The formation of pulses on the output bus 6 is made with the least noise immunity, since the trigger 27 is triggered by single pulses of interference and by the omission of pulses.

The formation of pulses on the output bus 23 is made with greater noise immunity than on the output bus 6, since pulses are not formed on single interference pulses. However, the noise immunity on the output bus 23 is worse than on the output bus 20, because a false pulse formation occurs in the gaps (Fig. 2k).

Claims (1)

The invention relates to a pulse technique and can be used in pulse signal processing devices. The purpose of the invention is to improve the noise immunity to the skip of input pulses. FIG. 1 shows the functional electrical circuit of the device; in fig. 2 - time diagrams of his work. The converter of the pulse train to the rectangular pulse contains an input bus I connected to the input of the waiting multivibrator 2, to the input of the delay element 3, to the first input of the first element 4, and to the input of the first trigger, the forward output of which is connected to the second input of the first element 4 and with the first input of the second element AND 5, inverse with the first output bus 6, the first installation input with the first installation input of the second trigger 7, the output of the inhibit element 8 and the first input of the first element OR 9, the second installation input is connected with the second setup input of the trigger 7, the input bus 10 "Reset and the first input of the second element OR 11, the second input of which is connected to the output of the first counter 12, and the output to the first input of the third element OR 13, the installation input of the second counter 14, the installation input of the third trigger 15, / -input the fourth trigger 16, the installation inputs of the third 17 and fourth 18 counters and the input of the fifth trigger 19, the inverse output of which is connected to the second output bus 20, and the S-input - the output of the third element And 21, the first input whom with the output of the counter 14, and the second input with the first input of the fourth element I 22 and the direct output of the trigger 7, the inverse output of which is connected to the third output terminal 23, and the counting input with the output of the element 4, the output of the generator 24 reference pulses are connected with the second input element AND 22 and the second input element AND 5, the output of which is connected to the counting inputs of counters 12 and 14 and the counting input of counter 18, the control input of which is connected to the forward output of the trigger 15, and the output to the first input of the element OR NOT 25, the second input of which is connected to the output ohm counter 17, and the output with the first input of the fifth element And 26 and the first input of the prohibition element 8, the prohibiting entrance of which is connected to the output of the waiting multivibrator 2 and the second input of the element 26, and the second input with the forward output of the trigger 16, S -input which is connected to the output of the element And 26, the installation input of the counter 12 is connected to the output of the element OR 13, the second input of which is connected to the output of the element 3 delay and the second input of the element OR 9, the output of which is connected to the counting input of the trigger 15, the inverse output of which is connected with the manager th input of the counter 17, the count input coupled to an output AND gate 22. The counters 17 and 18 - Reversible, triggers 27, 7, 15, 16, 19 may be formed on chips 133TV1. The device works as follows. The initialization of the elements is effected by applying a reset pulse to the input bus 10. The initial state of the triggers 27, 7, 15, 16, 19 is "O, counters 12 and 14 are all" O. The counters 17 and 18 in the initial state are recorded with a direct code proportional to D7 / 2, where LH is the duration of the pulses of the waiting multivibrator 2 (Fig. 26). The duration of the counters overflow pulses is equal to the duration of the pulse reference pulses. The triggers 27, 7, 15, 16, and 19 are switched on the back edges of the pulses at the single and counting inputs. The reversible counters 17 and 18 operate in the addition mode, if the control input has a potential of the upper level, and in the subtraction mode, if the potential of the low level is at the control input. The modules are reversible counts; cokes 17 and 18 are determined by the formula M, il ± llf, where / - is the maximum number of a number of missed pulses; Gchakg - the largest period of the following impulses; / 0 period of reference pulses. The temporal intervals between the bursts of pulses must satisfy the inequality: Г „(/ Ч-1) -7.,., Кс-. A pack of n pulses, the period of which can vary from pack to pack within (Gmin-Gchaks), goes to the conversion bus 1 (Fig. 2a). At the output of the waiting multivibrator 2, a packet of strobe pulses (Fig. 26) is formed, the duration of the DW, determined by the given instability of the period 67 D7-B7-Gmax. The first impulse of the rear edge switch switches to "1 flip-flop 27 (Fig. 2i), which allows the input of reference pulses to the inputs of counters 12 and 14, counting time intervals Tz, and to the input of the reversible counter 18, operating in subtraction mode. After a time LH / 2, the delay element 3 generates a first delayed pulse (Fig. 2c), which switches the trigger 15 into "1 (Fig. 26). At this moment, the code "00 ... 01 is stored in the counter 18 and it starts counting reference pulses in the addition mode, measuring the interval T between the first and second impulses of the packs. By the time the second delayed pulse arrives, the counter 18 counts / Ci PULSES - + The second burst pulse switches the trigger 7 to "1 (Fig. 2k), which allows the arrival of reference pulses to the counting input of the reversing counter 17. At the time the trigger 15 switches to" O " the counter 17 stores the code "00 ... 01 and it begins to measure the interval T2 between the second and third pulses of the packet. When K1 K2, T1 T2 is equal, overflow of the counter 18 operating in the subtraction mode occurs. An overflow pulse is generated when the counter reaches the state "00 ... O at the moment the third pulse arrives (Fig. 2e). At the same time, at the output of the AND element 26 a pulse is formed, switching the trigger 16 into "1. Measuring and comparing two orders of the following intervals with the help of reversible counters 17 and 18 is necessary to reliably determine the follow-up period in the event of loss of input pulses. In the case of the skip of pulses, the T, Tz intervals are unequal, therefore the overflow pulse does not form (at) or forms, but does not coincide with the third gate-pulse (at). Then the switching of the trigger 16 to "1 occurs when any two are equal, in addition the following intervals Γ, | 7, The measured value of the follow-up period is necessary for the subsequent recovery of the missed burst pulses. The trigger 16 allows the recovery of the missed impulses of a pack produced by the element S "Prohibition. It transmits overflow pulses when the input pulses and the strobe pulses are skipped (Fig. 2e). If a missed pulse is missed, counters 17 and 18 form / overflow pulses, which at intervals T arrive at the counting input of trigger 15. The first pulse after skipping a pack of pulses again synchronizes trigger 15 with respect to the pulses of the packet. The recovered burst pulses are reset to "On the trigger 27 and 7, which generate pulses on the output tires 6 and 23. The delay time Tc, relative to the first burst of the burst, is counted in the counter 14, which counts the reference pulses. The delay time is determined by the expression G:. | (/ - | -1) -7max UI | ./o, where M | - counter module 14. The overflow pulse of the counter 14 (Fig. 2h) switches the trigger 19 to "1 if the packet consists of several pulses () (Fig. 2n). If a single interference pulse arrives, the overflow pulse is not transmitted by element 21, since trigger 7 remains in the state "O" and the formation of the leading edge of the pulse on the output bus 20 does not occur. The formation of the trailing edge of the pulse on the output bus 20 is effected by the trigger 19 by the overflow pulse of the counter 12 after the time Tc2 relative to the last burst of the stack that dropped the counter into "O. For a tricky conversion of a burst of pulses with a duration of To, the counter modules 14 and 12 are chosen equal, which ensures that the delay times Gz1 7z2 are equal, then Guo 7out2 and the formation of pulses on the output bus 20 is more reliable than on the output tires 16 and 23, since the introduction of a delay during the formation of both fronts of the pulse at the output of the trigger 19 provides high noise immunity to the skips of the input pulses, both single and group (Fig. 2l). The formation of pulses on the output bus 6 is performed with the least noise immunity, since the trigger 27 is triggered by single impulses of interference and by skip pulses. The formation of pulses on the output bus 23 is performed with greater noise immunity than on the output bus 6, since no impulses are generated by single impulses of interference. However, noise immunity on the output bus 23 is worse than on the output bus 20, because a false pulse formation occurs on the passes (Fig. 2k). The invention of the converter of a burst of pulses into a rectangular pulse containing the first trigger, the first output of which is connected to the first input of the first reversible counter, and the second output - to the first input of the second reversible counter, the output of which is connected to the first input of the OR-NOT element, the second input of which connected to the output of the first reversible counter, the second input of which is connected to the output of the first element I, the first input of which is connected to the output of the reference pulse generator, and the second input to the first output of watts trigger, the second output of which is connected to the first output bus, and the first input to the first input of the third trigger, the first output of which is connected to the first input of the second element I, the second output to the second output bus, and the second input to the input input bus, differing in that, in order to improve the noise immunity of the device, three elements OR, third, fourth and fifth elements are introduced into it, fourth and fifth triggers, third and fourth pulse counters, a prohibition element, a waiting multivibrator, an element delays which are input th is connected to an input bus, the input monostable multivibrator and the first input of the third AND gate, and the output is with the first inputs of the first and second ele, OR, the output of the first element OR is connected to the first input of the first trigger, and the second input to the first input of the second trigger and the output of the inhibit element, the first input of which is connected to the output of the waiting multivibrator and the first input the fourth element is AND, the second input is connected to the output of the OR element - NOT and the second input of the fourth element is AND, and the third input is connected to the output of the fourth trigger, | the first input of which is connected to the output of the fourth element AND, and the second input - to the third input of the first receiver counterpart, the second input of the first trigger, the first input of the third pulse counter, the second input of the second OR element, the output of the third OR element, the first input of the fifth trigger, the second input of the second reversible counter, the third input of which is connected to the output of the second And element, the second input the third counter and the first input of the fourth counter, the second input of which is connected to the output of the second OR element, and the output to the first input of the third OR element, the second input of which is connected to the “Reset, third” they input the third trigger and the second input of the second trigger, the third input of which is connected to the output of the third element And the second input of which is connected to the first input of the second element And the second input of which is connected to the output of the reference pulse generator, the output of the third pulse counter is connected to the first input p the element And, the second input of which is connected to the second input of the first element And, and the output with the second input of the fifth trigger, the output of which is connected to the third output bus. . P Q (L I I I I I I I I I I I Jil.