SU1325677A1 - Pulse synchronizing device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is to increase the reliability of the device. It contains a reversible counter 2 pulses, the element OR 3, the element AND-NOT 5, and the bus 6-8 clock pulses, control and output. The introduction of synchronizer 1, the divider 4 frequencies and the formation of new functional connections allows temporarily spreading the pulses at the counting inputs of the reversible counter 2 pulses. 1 il. (L-ЖИi оi® d .J 8 о оa 1C SP a

Description

The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to increase the reliability of operation by temporarily spacing the pulses at the counting inputs of the reversible pulse counter.

The schematic diagram of the device is shown on the black card.

The device for synchronizing pulses contains synchronizer 1, reversible counter 2, element OR

ten

The initial state of counter 2 is zero. The output of element 3 is supported by a zero signal, which prohibits the passage of pulses through element 5 to the bus 8. At the output of divider k, pulses are formed with a frequency, where fjj is the frequency of the clock signal, and N is the division factor of divider 4.

The device is reset to its initial state automatically after it is turned on. If, when turned on, counter 2 is in a state other than zero, then at the output of element 3, the divider frequency 4, the element IS NOT 5, 5 sets a single signal.

which permits the arrival of pulses to the subtracting input of counter -2, which sets it to the zero state.

the first input of which is connected through a frequency divider 4 to the 6 clock pulse bus and to the first input of synchronizer 1, the second input of which is connected to the control bus 7, the output to the summing counting input of the reversing counter 2, the subtracting counting input of which is connected to the output bus 8 and the output element AND-NOT 5, the second input of which (Connected to the output of the element OR 5, the inputs of which are connected to the corresponding outputs of the reversible counter 2.

Synchronizer 1 contains the first 9, second 10, third 11 D-flip-flops, the element AND NOT 12 and the inverter 13, the input of which is connected to the first input

the synchronizer with the C input of the first 9 and the third 1 D-flip-flops, the output with the C-input of the second trigger 10, the direct output of which is connected to the D-BXO- house of the third D-flip-flop 11 and the first input of the AND-NOT 12 element , the output is with the synchronizer 1 output, the second input is with the inverse output of the third D-flip-flop 1I, the D-input of the second D-flip-flop 10 is connected to the direct output of the first D-flip-flop 9, the D-input of which is connected to the second input of the synchronizer 1.

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which permits the arrival of pulses to the subtracting input of counter -2, which sets it to the zero state.

When a pulse is received on the bus 7, the synchronizer 1 generates a single pulse along its leading edge, which coincides in time with the pause of the clock pulse.

Upon arrival at the input of a bundle of K pulses with a following frequency in a bundle equal to or less than f, the summing input of counter 2 goes to the pulses. A single signal appears at the output of element 3 and is present until the same number of K pulses with a frequency that are simultaneously transmitted to the output of the device arrive at the counter via the subtracting input.

. The device preliminarily assigns the synchronized pulse to the pause of the clock signal in order to separate in time the pulses acting on the addition and subtraction inputs of the counter, thereby eliminating the malfunction of the counter, which leads to unreliability of the output information of the device.

Due to the synchronization of the input

When applying to the input of the synchronizer pulses N-M clock pulse that

1 pulse signal, the latter is delayed by D-triggers 9-11, while at the output of the element AND-NOT 12 an inverse pulse is formed, important in cases when the receiving device is fast N times lower than the speed of the transmitting device, the frequency of the input pulse

cash, coinciding with the pause clock 50 owls in a pack can reach f, and

signal.

The synchronizer operation is not disturbed if cHrHaji with transients on the fronts with a duration of no more than the duration of the clock signal period is applied to its input.

The device works as follows.

The initial state of counter 2 is zero. The output of element 3 is supported by a zero signal, which prohibits the passage of pulses through element 5 to the bus 8. At the output of divider k, pulses are formed with a frequency, where fjj is the frequency of the clock signal, and N is the division factor of divider 4.

The device is reset to its initial state automatically after it is turned on. If, when turned on, counter 2 is in a state other than zero, a single signal is set at the element output.

which permits the arrival of pulses to the subtracting input of counter -2, which sets it to the zero state.

When a pulse is received on the bus 7, the synchronizer 1 generates a single pulse along its leading edge, which coincides in time with the pause of the clock pulse.

When arriving at the input of a pack of K pulses with a following frequency in a pack equal to or less than f, the summing input of the counter 2 goes to the pulses. A single signal appears at the output of element 3 and is present until K pulses of a frequency that are simultaneously transmitted to the output of the device also arrive at the counter via the subtracting input.

. The device preliminarily assigns the synchronized pulse to the pause of the clock signal in order to separate in time the pulses acting on the addition and subtraction inputs of the counter, thereby eliminating the malfunction of the counter, which leads to unreliability of the output information of the device.

Due to the synchronization of the input

important in those cases when the speed of the receiving device is N times lower than the speed of the transmitting device, the frequency of the input pulse frequency of the output pulses does not exceed fp / N,

i-p ,,, provided that smpul-K in a packet is not more than 2, where n is the counter width 2. Parameters 55 fо, N and n the devices are selected as follows:

fo f ,;

N N-f,

i ° 8eK ".

de f - maximum instant

the frequency of the pulses at the output of the transmitting device;

the permissible value of the frequency of the pulses at the input of the receiver; maximum number of pulses per packet at the output of the transmitting device.

f mom

Claims (1)

Invention Formula A device for synchronizing pulses containing a reversible pulse counter, the outputs of which are connected to the corresponding inputs Editor G.Gerber Order 3123/54 Compiled by T. Sokolova Tehred A. Kravchuk Corrector Circulation 901 Subscription VNISh State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 of the OR element, subtracting the counting input — with the output bus and with the output of the NAND element, control bus and clock pulses, characterized in that, in order to increase the reliability of operation, a synchronizer and a frequency divider, the output of which is connected to the first input of the element I-NOT, the input is from the clock pulse and the first input of the synchronizer, the second input of which is connected to the control interface, the output to the summing counting input of the reversible pulse counter, and the output of the OR element is connected; with the second input element NAND. Proofreader A.Zimokosov