SU1285582A1 - Device for generating rectangular pulses - Google Patents

Abstract

The invention relates to a pulsed technique and can be used in devices and systems of automation, telemechanics, communication and information gathering for the separation and formation of pulses in duration and phase. The purpose of the invention is to expand the functionality of the device. In the device containing pulse formers 1,2, elements II 4,6,9,10,11,12,15, first element OR 14, first delay element 5, tires: input pulses .18, reference pulses 19 and output 20, To achieve the goal, due to the restoration, at the output of the pulse duration and phase, a second delay element 7, a second SHSh 3 element, a D-flip-flop 8, RC-flip-flop 13, a reset bus 17 are introduced. 2). The duration of the pulses delivered by the formers 1.2 to their outputs must be such that, with allowable oscillations of the fronts of the input pulse in time relative to the reference, the duration of the pulses at the output of the I4 and I6 elements is no less necessary for a clear D-flip-flop 8. 1 3.p. f-ly, 3 ill. (O (X ate sd SH) id

Description

The invention relates to a pulse technique and can be used in devices and systems of automation, telemechanics, communication and information gathering for the allocation and generation of pulses in duration and phase.

The purpose of the invention is to expand the functionality of the device by restoring the duration and phase of the output pulse.

Figure 1 shows the functional electrical circuit of the device; in fig. 2 - electrical function. pulse driver circuit, example of implementation; on fig.Z - timing charts of the proposed device.

The device for forming rectangular pulses contains the first pulse shaper 1, the second shaper 2 pulses, the second element OR 3, to the second input of which the second output of the pulse shaper 2 is connected, the first element AND 4, the first input of which is connected to the first output of the pulse body 1 , the first delay element 5, the second element AND 6, the first input of which is connected to the input of the delay element 5 and the second output of the pulse shaper 1, the second delay element 7, clocked D-flip-flop 8, to the C input of which The output of element I6 is switched on, the third element I9, the first input of which is connected to the inverse output of the trigger 8, to the S-input of which the output of the element I4 is connected, the second input of which is connected to the first output of the driver 2 pulses, to the first input of the element OR 3 and to the second input Element I9, the fourth element And 10, the first input of which is connected to the output of the element OR 3, the second input of the element And 6 and the input of the delay element 7, the fifth element And 11, the sixth element And 12, the second input of which is connected to the output of the delay element 5, and the first - with the first entrance And P and with the direct output of a clocked D-trigger 8, the D-input of which is connected to the zero level of the power source, RS-flip-flop 13, to the S-input of which the output of the element 9 is connected, and to the R-input - output element I 10, the first element SHSh 14, the third entrance to

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the second is connected to the input of the element 12, the seventh, the element 15, the first input of which is connected to the second input of the element 11 and the output of the delay element 7, the counter 16 pulses, the summing input of which is connected to the output of the element II, the subtracting the output element AND 1S reset input - with R-input D-trigger Vis output element OR 14, and loan output - with the third input element And 9 and with the second input element And 10, the bus 17 reset, which is connected to the second input element OR 14, to the first input of which the transfer output of the counter of 16 pulses is connected, on 18 input pulses, which is connected to the input of the pulse former 1, the backbone pulse bus 19, which is connected to the input of the pulse former 2, the output bus 20, which is connected to the second input of the And 15 element and the trigger 13 output.

Shaper 1 (2) pulses (figure 2) contains the delay element 21, the element is NOT 22, the element is NOT 23, the element is And 24, to the second input of which is connected the output of the element HE 22, the element And 25, the first input of which is connected to the output of the element 21 delay and with the input element HE 22, and the second with the output element NO 23, the input of the imager is connected to the first input element AND 24, the input element 21 delay and to the input element; n- ta NOT 23, the first output is connected to the output element AND 24 , to the second you move the output of the element And 25 is connected.

The duration of the impulses t, caused by the formers 1 and 2 to the output faults, must be such that, with allowable fluctuations of the input pulse during the 2n relative to the reference, the pulse duration at the output of the AND 4 and 6 elements is no less necessary for a clear - batgaani trigger 8.

The magnitude of the delay T, element 5

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is chosen longer than the total response time of the element And 6 and trigger 8, i.e. such that in case of the falling edges of the input and reference pulses, the trigger 8 clearly closes the AND 12 element before the impulse arrives from the output of the element 5.

The magnitude of the delay T of element 7 is chosen as the outcome of the following conditions:

T, must be greater than the total time to trigger the element H 4 and the installation of the trigger 8 in a single position, i.e. such that by the time of the appearance of a pulse from the output of element 7, the trigger 8 clearly opens element 11 and in the event that the pulses corresponding to the leading edges of the input and reference pulses coincide in time;

tj must be longer than the total response time of AND 6 and the zero position of the trigger 8 at the clock input, i.e. such that by the time of the appearance of a pulse from the output of element 7, the trigger 8 clearly closes the element AND II when the pulse corresponding to the trailing edge of the input coincides with the pulse from the output of the element OR 3.

D-trigger 8 on the clock input and the counter 16 pulses on the summing and subtracting inputs triggers on the leading edges of the pulses received at these inputs. When pulses arrive at the installation inputs in the single position (S-inputs) of the flip-flops 8 and 13, the latter are set to the single position. When pulses arrive at the reset inputs (R-inputs) of the flip-flops 8 and 13 and the counter of 16 pulses, the latter are set to the zero position regardless of which signals act on their other inputs.

At the output of the loan (BR) of the counter 16 (the output of the overflow during subtraction) there is a signal if the contents of the counter 16 are equal to O and there is no pulse at the subtractive input.

At the output of the transfer (CR) of the counter 16 (overflow output upon summation) there is a signal if the counter is full, i.e. all triggers are in a single position, and there is no pulse at the summing input.

A zero power supply bus is connected to the information input of the trigger 8 and, as a result, upon receipt of a pulse to the clock input of the trigger 8, the latter is set to the zero position on the leading edge of the pulse.

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The third input element And 9 uttnepf, - ny, i.e. if there is a signal on this signal, the element is closed, and in the absence of a signal at this input, element And 9 works in accordance with the signals acting on the first and second inputs.

The delay time, the element 21 of the formers 1 and 2 pulses - is chosen equal to the duration of the pulses that are output to the outputs of these formers.

The time diagrams (Fig. 3) show the operation of the device during the posting to the bus 18 of an impulse coinciding in phase with the reference and equal in duration period of the reference impulses (first impulse, fig. 3), impulse coinciding in phase with the reference and equal in duration to the sum of the period and the duration of the supports -. pulse (second pulse, fig.Zg), pulse, coinciding i in phase with the reference, but not equal to any of the set durations (third pulse, fig.3 -b), pulse, not coinciding in phase with the reference (fourth pulse , FIG. 3 d) FIG. 3 and c show the signals at the first and second outputs of the driver 1, respectively, in FIG. 3 & and b shows the signals at the first and second outputs of the driver -2, respectively.

A device for forming rectangular pulses operates as follows.

The device analyzes the pulses arriving at the input bus 18, and if these pulses coincide in phase with the reference pulses and have one of the specified durations, then it forms, on the output bus, a pulse coinciding in phase with the reference pulse with a duration equal to the duration of the received pulse. The set values of pulse durations are equal to the duration of the reference pulse, equal to or a multiple of the period of the reference pulses and the sum of the duration of the reference pulse and a value that is a multiple of the period of the reference pulses.

Shaper 1 (2) impulse works as follows.

In the absence of a signal at the input, elements And 24 and 25 are closed at the first inputs and prepared for operation at the second inputs, since at the output

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The delay element 21 has no signal, and the outputs of the elements NOT and 23 receive signals.

When a signal appears at the input of the driver, the signal at the output of the HE element 23 disappears, the delay element 21 is triggered and the H 24 element is triggered, and a signal appears at the first output of the driver. After a time delay, a signal appears at the output of the delay element 21, and as a result, the signal at the output of the HE element 22 disappears, the AND 24 element shuts down and the signal ends at the first shaper output. Thus, at the first output of the imager, a pulse is formed that is equal in duration to the delay value of the element 21 and corresponds to the leading edge of the input signal from the imager.

At the time of the end of the signal at the input, the AND 24 element is obscured, and the signal at the output of the HE element 23 appears, And 25 is triggered, and a signal appears at the second output of the driver. After a time delay element 21 disappears

its output and closes the element And 25, the signal ends at the second output of the driver. Thus, at the second output of the imager, a pulse is formed, equal in duration to the delay value of the element 21 and corresponding to the falling edge of the input signal from the imager.

In the initial state of the device, the triggers 8 and 13 and the pulse counter 16 are in the zero position (Fig. 3, t, y). At the outputs of the pulse former, there are no pulses, the outputs of the pulse former 2 and the element OR 3 have pulses, corresponding to the fronts of the reference pulses, but the pulses corresponding to the fronts of the reference, do not pass to the outputs of the elements 4 and 6, since the first inputs of these elements have no pulses, nor to the outputs of the elements 9, 11 and 15 which are closed at least one front. The pulses from the output of the element OR 3 pass only through the element AND 10, confirming the zero position of the trigger 13. Setting the device to its initial state after turning off the power is detected by applying

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pulse to bus 17, in this case the trigger 8 and the pulse counter I6 are packaged to the zero position, the trigger 13 is set to zero position first after the counter 6 is set to the zero position by a pulse from the output of the OR 3 element.

Upon receipt of the input pulse 18 on the bus, which coincides in phase with the reference pulse, the pulses corresponding to the leading edges of the input and reference pulses coincide at the inputs of the element I 4 and the element 4 triggers (Fig. 3) and the pulse from its single trigger output 8 Opens the elements And 11 and 12 (fig.Zr 5c). At the same time, element 9 is additionally closed (Fig. 3a). Through the element And 11 pulses from the output of element 7

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delays (time delayed t

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the pulses corresponding to the fronts of the reference pulses, Fig. 3L) begin to arrive at the summing input of the counter 16 pulses and are fixed by it. The determination of the duration of the input pulse. At the moment of fixation of the first pulse from the output of element 11, counter 16 (fig. 3), the signal at its input disappears; and as a result, element 10 also closes and element 9 is prepared for opening (fig. 3 P, o) the end of the input pulse 5 at the second output of the driver I pulses a pulse appears corresponding to the falling edge of the input pulse and arriving at the input of the delay element 5 and the first input of the And 6 element. If the duration of the input pulse does not correspond to any of the set values, then after time t pulse with output element 5 goes through three elements

 Both 12 (FIG. 3c) and OR 14 both set the pulse counter 16 and the trigger 8 to zero. The device returned to its original state and is ready to receive and analyze the next input pulse. No pulse is output to the output bus.

If the duration of the input pulse corresponds to one of the set values, then the pulse corresponding to the trailing edge of the input pulse coincides in time with the pulse corresponding to one of the reference edges, the element is triggered.

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And 6 (FIG. 3m) and the trigger 8 is set to the zero position (FIG. 3) on the leading edge of the pulse from the output of the element AND 6, the element 9 is opened (FIG. 3 o) and elements 11 and 12 are closed, therefore the pulses from the outputs elements 5 and 7 do not pass to the outputs of the elements, respectively, AND 12 and P. In the pulse counter 16, the code of the input pulse duration remains recorded.Ec pulse corresponding to the trailing edge of the input coincides in time with the pulse corresponding to the leading edge of the reference one and at the vocal output driver 2 pulses still valid the pulse then triggered the element AND 9 (FIG. 3) and the trigger 13 (FIG. 3g) is set to the single position, the element 5 is opened and the pulse starts to form on the output bus 20. Through the element 15 the output pulses from element 7 start enter the subtracting input of the counter 16. Through the element AND 9 pulses from the first output of the driver 2 pulses confirm the single position of the trigger 13. At the moment of termination at the subtractive input of the counter 16 of the pulse which recorded the number O, a signal appears at the output of the counter 16 pulses ( fig.zu) closing The element is AND 9 and the element is opened AND 10, the first pulse after the appearance of the signal at the output of the counter 16 is a pulse from the output of the element OR 3 (Fig. 3) passes through the element AND 10 (fig. Zi) and sets the trigger 13 to zero

The position, on the output bus 20, has completed the formation of a pulse of a set duration and coinciding in phase with the reference one, the device has returned to its original state and is ready to receive and analyze the next pulse.

If the pulse corresponding to the falling edge of the input coincides in time with the pulse corresponding to the leading edge of the reference edge, but by the time the position of the trigger 8 is set to one, the pulse at the first output of the driver 2 pulse and the element 9 did not work, and the trigger 13 did not establish in the same position, then the next pulse from the first output of the driver 2 pulses

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passes through the element AND 9, the trigger 13 is set to a single position, on the output bus 20 begins the formation of a pulse. Further, similarly to that described, the formation of the output pulse is completed and terminated. Thus, in this case, the formation of the output pulse is performed with a delay for the period of the reference pulses.

If the pulse corresponding to the trailing edge of the input coincides in time with the pulse corresponding to the trailing edge of the reference one, then the element I triggers when a pulse appears at the first output of the driver 2 and then the formation of the output pulse is carried out similarly described. Thus,. in this case, a pulse of a set duration, coinciding in phase with the reference one, is formed with a delay of 5 pause times between the reference pulses by -5.

If the input pulse does not coincide in phase with the reference pulse, then the pulse corresponding to its leading edge does not coincide in time with the pulse corresponding to # 1 to the leading edge of the reference pulse, AND 4 does not trigger, at the moment the input pulse ends the second output of the pulse generator 1, the delay element 5 starts up and after time f, a pulse appears at the output of the element 5, after the end of which the device is in the initial position, no pulse is generated on the output bus 20.

If the pulse 18 arrives at the pulse that coincides in phase with the reference one, but exceeds the maximum set duration, T (2–2), where m is the period of the reference 1-pulses; k is the size of counter 16, then at the end of the summing input of counter 16 fpul, recording the number (I) in the counter, at its transfer output (CR) a signal appears that sets to zero position through the element OR 14 trigger 8 and the counter 16. At the moment of termination of the input pulse, a pulse appears at the second output of shaper 1, which after a time t, from the output of delay element 5

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on ptoron input element I 12, through which he does not pass. After the end of the pulse from the output of the element 5, the device is in the initial position; no pulse is generated on the output bus 20.

Claims (1)

1. A device for generating rectangular pulses containing the first and second pulse formers, the first element AND, to the first input of which the first output of the first pulse generator is connected, the first delay element, the second element AND, the first input of which is connected to the input of the first delay element and with the second output of the first pulse generator, the third element And, the second input of which is connected to the second input of the first element And and with the first output of the second pulse generator, the fourth, fifth, sixth and seventh ele And, the first element OR, to the third input of which is connected the output of the sixth element And, the pulse counter, the input pulse bus connected to the input of the first pulse driver, the reference pulse bus connected to the input of the second pulse driver, and the output bus, characterized in that , in order to extend the functionality at the expense of restoring the duration and phase of the pulse at the output, a second OR element, a second delay element, a clocked D-flip-flop, an RS flip-flop and a reset bus connected to the watts are introduced into it The first input of the first OR element, the first input of which is connected to the transfer output of a pulse counter, the reset input of which is connected to the output of the first OR element and to the R input of a clocked D trigger, whose direct output is connected to the first input of the fifth And element and to the first the input of the sixth element And, the second input of which is connected to the output of the first element for-; 15 , nperfO 20 25 holders, the output of the first element and the pdkdkltr, to the S-INPUT of a clocked D-flip-flop, the D-input of which is connected to the zero bus of the power source, and the C-input to the output of the second element And the delay element, with the output of the second element OR, and with the first input of the fourth element AND, the output of which is connected to the R input of the .RS trigger, the S input of which is connected to the output of the third element AND whose first input is connected to the inverse output of the D-trigger being clocked , and the third input - with the second input of the fourth element And in a yield loan pulse counter to the subtraction input of which is connected to the output of the seventh AND gate, whose first input is connected to the second input of the fifth AND gate and with the output of the second delay element, and the second input - to a direct output of RS-trigger with vy30 The input bus, the output of the fifth element I is connected to the summing input of the pulse counter, the first and second outputs of the second pulse former are connected respectively to the first and second inputs of the second element OR. 2, The device according to claim 1, about tl and - the fact that each of the pulse shapers includes a delay element, the first element is NOT, the second element is NOT, the first element is AND, the first input of which is connected to the input of the delay element, with the input of the second element NOT with the pulse driver input, the second element I, the second input of which is connected to the output of the second element NOT, the first output of the driver is connected to the output of the first element AND, to the second input of which the output of the first element NO is connected whose input is connected to the output of the delay element and with the first input of the second element I, the output of which is connected to the second output of the pulse former. 35 40 45 FIG. g pppppppppppppg