SU1211857A1 - Device for generating rectangular pulses - Google Patents

Abstract

The invention can be isolated in the systems of automation, telemechanics and data collection. The purpose of the invention is to improve the reliability of operation by preventing malfunctions due to the effects of interference occurring during the formation of an output 1 1-pulse. The device contains elements 1, 4 and 9, a generator of 2 pulses, a driver of 3 pulses of a falling front, a delay element 5, counters 6 and 1 O of pulses, a decryption unit 7, an encoder 8 and TINI P and 12 inputs and outputs. The decryption unit 7 can be made of a decoder with the elements OR at its outputs. The encoder 8 serves for the transformed signals from the outputs of block 7, corresponding to the set values taking into account the tolerance of the duration of the input signals, to the binary code of the set lengths. 1 il. c (C (L

Description

The invention relates to a pulse technique and can be used in devices and systems for automation, telemechanics and data collection.

The purpose of the invention is to increase the reliability of unit footing by preventing disruptions in operation due to the effect of interference occurring during the formation of the output pulse.

The drawing shows the functional electrical circuit of the device for generating right angle pulses.

I A device for generating rectangular pulses contains an element I 1, a generator 2, a pulse, a driver of 3 trailing edges, an element of AND 4, a delay element 5, to the input of which the output of the driver 3 is connected, the first pulse counter 6 of the pulses, the summing input of which is connected to the output element 4, decryption unit 7, to the informational inputs of which the bit outputs of the pulse counter 6 are connected, the overflow output when summed up is connected to the input of the element 4, the third input of which is connected to the driver input .3, with the output of the element I 1 and with the enable input of the interpreting unit 7, the encoder 8, the inputs of which are connected to the outputs of the interpreting unit 7, the element And 9, whose input is connected to the input of the element And 4 and with the output of the generator 2, the second pulse counter 10 , to the information inputs of which are connected, inputs of the encoder 8, input 7 bus 1 1, which is connected to the second input of the element AND 1, output bus 2 which is connected to the first input of the element And, with the output of the counter O and with the first input of the element And 9, output which is connected to your input counter Figure 10, the input of the information recording resolution in the parallel Vade, of which is connected to the reset input of the counter bis by the output of the delay element 5.

The decryption unit 7 is designed to decrypt the contents of the counter 6 if there is no signal at the permission input (i.e. the enable input of the decryption unit 7 is inverse). With the contents of the counter 6 equal to the set values taking into account the tolerance, block 7 outputs signal to one of the outputs,

The decryption unit 7 may consist of a decoder with the elements OR

on his exits.

The encoder 8 is designed to convert signals with the output of the decryption block 7 corresponding to the set values, taking into account the tolerance of the duration of the input: signals (set values of the contents of counter 6) into the binary code of the set durations.

Counter 6 by totalizing input

and the counter 10 on the subtractive input operates from the leading edges of the pulses arriving at these inputs. Counter 6 at the reset input operates on the falling edge of incoming signals.

pulses in the case when the pulse counters do not have reset inputs operating on the pulse front, allowing the counter to be reset on the falling edge of the pulse, in this case the signal to the counter input goes through the included delay element, the delay value of which is set equal to the pulse duration, arriving at the entrance

reset.

The imaging unit 3 outputs on the falling edge of the pulse received at its input, a pulse whose duration is chosen sufficient for the accurate operation of counters 6 and 10.

The delay i of element 5 is chosen based on the fact that the impulse given by shaper 3 must arrive at the V-input of counter 10 after a clear sequence of the sequential chain: element 4, counter 6, decrypt block 7, encoder 8.

 The frequency of the pulses of the oscillator 2 is selected from the required accuracy of recognition of the input pulses and their reproduction at the output.

The device for forming of rectangular pulses operates as follows.

In the initial state, the counters 6 and 10 are in the zero position, at the overflow output with the subtraction (P) of the counter 10 and on the output bus 12 there is a zero signal, the closing element And 9 and the opening element And 1.

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An output on the input bus 1 of the I pulse through the And 1 element opens the And 4 element and the pulses of the generator 2 begin to flow to the summing input of the counter 6. The duration of the input pulse is converted into a code of the number of pulses of the generator 2, At the moment the pulse ends on the input bus I1 closes the element AND 4, decryption unit 7 opens and shaper 3 issues a pulse, triggering delay element 5. If the duration of the input pulse on bus II is in one of the set limits, a signal appears on one of the outlets The one of the decryption unit 7 is fed to one of the inputs of the encoder 8, on the outputs of which a binary code is set, corresponding to the first duration. After a time, a pulse from the output of the delay element 5 is fed to the reset input of counter 6 and to the VHSD to enable information recording in parallel form of counter 0, into which a binary code of a set duration is written, which is at the outputs of the encoder 8, at the output of overflow during extinction the counter 10 and the output bus 12, an impulse appears, the element And 9 opens and the element 1 closes. On the output bus 12 the formation of the output impulse begins, At the moment of the end of the pulse from the output of the delay element 5, the counter 6 sets with the zero position. Through the element And 9, the pulses of the generator 2 begin to flow to the subtracting input of the counter 10, i.e. testing of the set pulse duration occurs. At the moment of termination on the subtracting input of the pulse counter 10, the number 0 recorded in the counter 10, the overflow output signal disappears when the counter 10 is subtracted, the AND 1 element opens, the AND 9 element closes, and the output pulse ends on the output bus 12. The device is ready for the next cycle work. Thus, when taking

+ lt

impulse, duration t,

- it

The output generates an output pulse of duration t ,. .

11857

If the duration of the input pulse on bus 1I does not correspond to any of the specified durations taking into account the tolerance, then at the time of the end of the input pulse, as described above, the AND 4 element closes, the driver 3 issues a pulse that triggers the delay element 5, and opens deciphering

10, block 7, but no signal appears on any of its latencies, and, accordingly, a zero code also remains at the outputs of the encoder 8. The pulse from the output of the delay element 5 writes to counter 10 a zero code,

those. the latter will not change its position and a zero signal remains on the output bus 12. On its trailing edge, the impulse from the output of the element for –20 of the support 5 sets the counter 6 to the zero position. The device returns to its original position; no pulses are output to the output bus.

25 If the duration of the input pulse on bus 11 exceeds the maximum code value that can be written to counter 6, then counter 6 is filled completely and at the time of closing at the summing input of the pulse that has written to counter 6 the number 11 .., at the overflow output with summation (P.) a signal appears that terminates the AND 4 and element.

Therefore, before the end of the input pulse, no pulse is received at the input of counter 6. At the time of the windows "- the pulse on the input bus 11, the device returns to its original state

the state on the output bus 12 is not impulse.

If, after the end of the pulse on the input bus 11, the duration of which corresponds to one of the set values, taking into account the tolerance), but before the end of the formation of the output pulse on the bus 11, the interference pulses are present, then, since element I 1 is closed at this time, these pulses not

will be passed to the input of the imager 2 and the device will not fail.

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Claims (1)

Invention Formula A device for forming rectangular pulses, comprising the first And element, an impulse generator 51 The second driver, the first element of which is connected to the output of the pulse generator, the first pulse counter, the summing input of which is connected to the output of the second element, and the decryption unit whose information inputs are connected to the bit outputs of the first a pulse counter, the first travel of the first element I is connected to the output bus, characterized in that, in order to improve the reliability of operation, a delay element, an encoder, a third AND element, and a second counter imp lsov whose output is connected to the output line and the first input of the third AND gate, a second input coupled to the first input vto211857U element M, to the second input of which is connected the output of the first pulse counter, the reset input of which is connected to input 5 of the recording resolution of the second pulse counter and the output of the delay element, to the input of which is connected the output of the leading edge pulse generator, whose input 10 is connected to the third input of the second element I, with the output of the first element I and the permission input of the decryption unit whose outputs are connected to the inputs of the encoder, the strokes of which are connected to the information inputs of the second counter 1 pulses, to the subtracting input of which the output of the third element I is connected, the bus is connected 20 second entrance of the first element I.