SU1319263A1 - Variable pulse delay device - Google Patents

Abstract

The invention can be used for delaying pulses in various automation, remote control, and computing devices. The purpose of the invention is to increase the reliability and simplify the device. The device contains a pulse generator 1, elements AND 4-7, counters 8-10 pulses and bus 13-15 delayed pulses, control pulses and output pulses, respectively. The introduction of the elements 2 and 11, the driver of the 3 pulses of the leading edge, the element 12 and the new connections made it possible to exclude from the known device two triggers, a block for detecting the coincidence of codes and a decoder zero. The use of these elements made the device more complicated, increased the range of the generated values of the delay and the duration of the pulses, as well as the width of the pulse counters. 1 il. (L 00 with to C5 oo

Description

The invention relates to a pulse technique and can be used to delay pulses in various automation, remote control, and computing devices.

The purpose of the invention is to increase reliability by simplifying the device.

The goal is achieved by the fact that, instead of elements whose complexity increases with increasing magnitude of the delay

proportional to the duration of the control pulse. The recorded code is stored in counter 9 until a new control pulse is received on bus 14.

When a pulse arrives at the bus 13, a zero signal appears at the output of the element HE 2, which closes the additional element 6, and the driver 3 generates a pulse arriving at the recording input of the counter 10 and recording in this account 15

signals, such as a block of coincidence codes, Yuchik, the contents of pulse counter 9 (code decoder zero, two NOT elements, delay pulses are entered). The output of the counter 10

a single signal appears, as a result, at the output of the element NOT 11 a zero signal appears, closing the element 12 at the second input, and the element 4 is opened, through which the pulses of the generator 1 begin to pass to the subtracting input of the counter 10 pulses and to the second input element 5, which is opened by the input pulse from bus 13. With the output NOT AND, element 12, the bus 13 for 20 and the element AND 5 pulses are received by the impulses held, the bus 14 is impulse to the summing input of the counter 8 pulses. After the counter 8 is detected by the first incoming pulse, a single signal appears at the loan output of this counter. Next, we consider three cases of the relationship between the duration of the input pulse and the magnitude of the delay.

Input pulse duration is less than

the element And, the driver of the pulses of the leading edge and new connections.

The drawing shows a functional diagram of the device.

The controllable pulse delay device contains a pulse generator 1, the first element is NOT 2, a forward pulse driver 3, elements AND 4-7, counters 8-10 pulses, control ales, output bus 15. In the initial state, the device controls the pulse delay given by zeroing the counters 8 and 10 pulses.

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Counters 8-10 pulses have the following modes of operation.

Counter 8 pulses on the summing and subtracting inputs and the counter 10 and the magnitude of the delay.

Impulse on tire 13 in this case

pulses at the counting input, which is -..., terminates before the subtractive appears, work on the difference of the O-1 signals arriving at these inputs. The counter 9 pulses on the counting input, which is summing, operates on the 1-O signal drop, and on the reset input, on the O-1 signal drop.

A zero signal appears at the output of the counters 8 and 10 pulses if the contents of the corresponding counter are zero and there is no impulse at the subtracting input of the counter.

35

The second signal is at the output of the loan of the counter 0. At the moment of the pulse ending at the bus 13, the element 5 is closed and the pulses from the output of the element 4 do not pass more to the summing input of the counter 8, moreover, a single signal appears at the output of the element 2 the opening element of the first input is AND 6. At the moment of the end, at the subtractive input of the counter 10 a pulse recorded in the counter 10 is the number "O, the zero sign appears in its counter 10 pulses of the code arriving at its information inputs.

The shaper of 3 pulses of the front 40 is closed, the element 4 is closed, it appears - the front produces a pulse on the difference O-1c, a single signal at the output of its input element, a duration of minimum NOT 11 and the element 12 triggers.

A single signal to the output

bus 15 and the element 6 completely opens, through which the pulses of the generator of the delay 1 of the impeller 1 begin to pass to the subtrac- tion of the pulses as follows: the common input of the counter 8 pulses. In my pass to the bus 13, the delayed end of the subtractive input of countable pulses is fed to the bus 14 pulse, the pulse 8 of the pulse recorded in the counter 8 whose duration is equal to the set-number "O at its input loan appears

my magnitude of the delay. On the leading edge - 50 zero signal. Element closes AND 12

the pulse from the bus 14, the pulse counter 9 is set to the zero position, the E 7 element simultaneously opens and the generator 1 pulses start to arrive at the summing input of the counter 9,

a single signal terminates at the output bus 15, element I 6 closes. The device returns to its original state, a delayed pulse is formed on the output bus 15, the length of which is fixed at the falling edge 55 time equal to the input counter 9. At the end of the pulse pulse.

The duration of the input pulse is equal to the delay.

element 7 on the bus 14 is closed, while the counter 9 contains the code.

proportional to the duration of the control pulse. The recorded code is stored in counter 9 until a new control pulse is received on bus 14.

When a pulse arrives at the bus 13, a zero signal appears at the output of the element HE 2, which additionally closes the element 6, and the driver 3 generates a pulse arriving at the recording input of the counter 10 and recording the amount of delay into this account.

Impulse on tire 13 in this case

ends sooner than zero

The second signal is at the output of the loan of the counter 0. At the moment of the pulse ending at the bus 13, the element 5 is closed and the pulses from the output of the element 4 do not pass more to the summing input of the counter 8, moreover, a single signal appears at the output of the element 2 the opening element AND 6 at the first input. At the moment of the end of the pulse 10 at the subtractive input, the number recorded in the counter 10 is "O, the zero signal appears at its output of the loan, the element 4 closes, and a single signal appears at the output In this case, zero appears at the same time. drove the output of the counter 10 and the pulse ends at the input HJHHe 13. Due to the end of the impulse on the bus 13, the element AND 5, closes, and due to the appearance of a zero signal at the output of the loan of the counter 10 pulses, the element 4 closes (at the second input element 5 stops the generator pulse 1), a single signal appears at the output of the element II, element 12 triggers, and a single signal appears at its output and on the output bus 15. Element I 6 opens and the generator 8 impulses start to pass to the subtracting input of counter 8. Next, the device operates as described above and outputs a pulse to the output pin 15, the length of which is equal to the input and delay duration; :: lk iia value of the set delay.

The duration of the input pulse is greater than the delay value.

In this case, before the end of the pulse on bus 13, a zero signal appears at the output of the loan of counter 0. A single signal appears at the output of the HE II element, the element I 12 triggers, and at its output and on the output bus 15 there appears a single the signal that opens element I 6 at one of the inputs, but the generator 1 pulses do not pass through it, since its other input does not receive a zero signal from the output of NOT 2.

At the same time, the element I4 is closed and the generator 1 pulses do not pass to the reading of the counter 10 and to the second input of the element 5, the pulses to the summing input of the counter 8 pulses are stopped. Thus, at the time of the end of the delay time, the formation of the output pulse begins and the conversion of the duration of the input pulse to the code recorded in the counter 8, in which the delay time value code remains, stops. At the moment of the end of the pulse on the bus 13, the element And 5 closes on the first input and the element 6 opens completely, through which the pulses of the generator 1 begin to flow to the subtracting input of the counter 8 pulses. At the moment of termination at the subtracting input of the pulse, the number "O" appears in counter 8, the zero signal at the output of this counter's loan, element I 12 closes, a single signal ends on bus 15 and element AND 6 closes. in the initial state, an impulse is output to the input bus 15.

Compiled by A. Contour

Editor A. SaboTehred I. VeresKorrektor I. L ska

Order 2530/55 Circulation 901 Subscription

BfiHl lilH of the State Council of SSS R but did: izobrsni .:: and: O: K; I: g; th

1 1.3 (). 35, L'Aoskva, F - 35, Raushsk nab. D. .t- 1 | 1 () ectnp. i

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whose duration is equal to l.:. : -GSL; -; Og: and the input pulse and which is delayed ;: by the value of the delay time by o-riioiiiiiniio to the input pulse.

Claims (1)

Thus, the introduction of d /jo.NieH- tov NOT, the former H.Miiy.i.vjtu; The front of the front, the element And, and the new connections will allow you to remove two triggers from the well-known SlTiKi line, the detection unit ,. lg; ;:; codes and descrambler zero, ns; It is useful: kp:; -; which leads to a significant complication of the device with an increase in the range of the generated values of the delay and d.1.ge, 1-pulse, and, as a consequence, with in. - the calculation of the counter size; impch.tatsov Invention Formula A controllable pulse delay device containing the generator, the first, second, third and even-ness cops I. the first counter, 1msk of the su.mming input is the pithorn-o, the output of the first element is And, nepsbifi of which is connected i bus zachorzhiv; nymi pulses, and to the subtracting input of the first pulse counter per pulse 2; s move the second element I. the second ct pulse pulse, to the counting input of which the output of the third element I is connected. iicpHiiifi whose input is connected to the first: 1-: Bypass; 5th second and fourth elementov 1 and the output of the pulse generator, and the second th 4) 401 in; five 0 five 0 0 ka pulses and bus 1; . :) Owls control, third pulse counter, 1H1 1st input which is connected to the output; 1st of the fourth element I, the output bus connected to the second input of the second element And, characterized in that, in order to increase reliability simplifying the device, the front-edge pulse former, the fifth AND element, the first and second HH units, are entered into it. moreover, the output of the first W-. connected to the third entrance of the second .meig II. and the input is from the first input of the first eimention I and the input of the front-end NMR pulse generator, the output of the KOTopoi o is connected to the input of the recording of the third pulse counter, the information input | 1 of the KOTopoi o is connected to the outputs of the second one counts and pulses, and the output 3ae, Nia - from the second input of the fourth element And, the output of which is connected to the second input of the first element I. And to the input of the second element NOT, the output of which is connected to the first input of the fifth element 1. : the input of which is connected to the SEND J:; 0.; i the first pulse counter, and the exit - with the output bus.