SU1713104A1 - Converter of binary code to numeric-pulse code - Google Patents

Abstract

The invention relates to automation and impulse technology and can be used in electronics, in automatic control and regulation systems, in coding and communication devices. The purpose of the invention is to increase reliability and speed. The converter contains an information channel selection node 1 consisting of a zero decoder 2, a binary pulse counter 3, a decoder 4, an AND-NE element 5 and a HE element 6, a pulse generator 7, and in information channels 8, 9, 10, respectively, reversing pulse counters 11 , 12,13, decoders zero 14, 15,16, elements OR-NOT 17,18,19, elements AND-NOT 20, 21, 22, delay elements 23, 24, 25, elements OR 26, 27. 28 and element OR 29.1 il. ^ V • h ^^ The invention relates to automation and pulse technology and can be used in radio electronics, in automatic systems control and regulation, in the coding and communication devices. A number-pulse code generator is known which contains a driver unit made using a switch, a button, a capacitor, an asymmetrical multivibrator and a power amplifier. The disadvantage of such a generator is a limitation in the representation of the input information, lack of independence of input of information in relation to its exit from the generator, lack of a fixed time delay between codes, low speed. Closest to the proposed The invention is a binary-to-pulse code converter that contains a pulse generator, a zero decoder, a first and second AND-NOT element, a trigger whose direct output is connected to the output of a pulse generator, and the output of a frequency divider is connected to a subtracting input the pulse counter is the information output of the converter whose recording record is connected to the trigger input, the reset input of which is connected to the pulse counter reset input, the first group of outputs of which is connected to the desh inputs Rattor zero, the output of which is connected to the inhibiting input of the frequency divider and the C-input of the trigger, the inverse output of which is connected to the first inputs of the first and second AND-NOT elements, the outputs of which are connected respectively to the second input of the second AND-NOT element and the pulse addition counter input , the second group of outputs of which is connected to the group of inputs peo-t > & & > &

Description

The Boro of the NAND element, the output of which is the control output of the converter, the information inputs of which are connected to the information inputs of the pulse counter, the output of the pulse generator is connected to the third input of the second NAND element, the input of the logic zero of the converter is connected to the D input of the trigger.

However, in this converter, the input of new information is possible only after clearing the reversible pulse counter, which imposes a limit on the rate at which information is entered into the converter and its speed. The converter also does not provide a predetermined delay between the number of pulse codes, which can lead to overlapping, combining the output codes, and consequently, to obtaining a false code at the output of the converter.

The aim of the invention is to increase the reliability and speed of the converter by accelerating the rate of input of information, matching input and output information and marking information packages.

The goal is achieved by converting a binary code into a pulse code containing a pulse generator and, in the first information channel, a reversible pulse counter, whose information outputs are connected to the inputs of the zero decoder, and the NAND element, the output of the pulse generator is connected to the first input of the element NAND, the information inputs and the reset input of the reversible counter are respectively information inputs and the reset input of the converter; according to the invention a multi-pass element is introduced LI, information channel selection node, performed on the zero decoder, binary pulse counter, decoder, NOT element and AND-NOT element, the zero decoder output is connected to the counting input of the binary pulse counter, the outputs of which are connected to the decoder inputs, the output of the NOT connection 1 pin with the first input of the NAND element, the output of which is connected to the reset input of the binary counter of the impulse, the output of the last digit of the decoder is connected to the second input of the NAND element, the input of the element is NOT the reset input of the converter, The zero decoder s are connected to the information inputs of the N-1 converter (N is the number of code words to be converted) of information channels made similar to the first one, and the OR element, the delay element and the OR-NOT element, the first input of the OR-NO element are additionally added to each information channel the first information channel is connected to the output of the pulse generator; in each information channel, the overflow output of the reversible pulse counter is connected to the first input of the OR element through the output element OR of each previous information channel, starting with the first one, is connected to the first inputs of the OR element and the NAND element of the subsequent information channel, on each information channel, the output of the zero decoder is connected to the second inputs of the OR element and the NAND element, the output of which connected to the second input of the OR element, the output of the OR-NOT element is connected to the subtractive input of the reversible pulse counter and to the corresponding input of the multi-input element OR, the output of which and the output of the OR element of the last information channel The La are the first and second outputs of the converter, the decoder outputs are connected to the recording inputs of the reversible pulse counters of the respective information channels, the information inputs and the reset inputs of the reversible counters N - 1 information channels are connected to the information inputs and the reset input of the converter, respectively.

The drawing shows a structural diagram of the proposed converter of a binary code into a pulse code.

The converter contains a node for selecting information channel 1, consisting of input decoder zero 2, binary pulse counter 3, decoder 4, AND-NE element 5, HE 6, pulse generator 7, first channel 8, second channel 9 and N channel 10, consisting respectively of reversible pulse counters 11,12, 13, decoder zero 14,15,16, elements OR-H 17, 18, 19, elements AND-HE 20, 21, 22, delay elements 23, 24, 25, elements OR 26, 27, 28 and the element OR 29.

In this case, the information inputs of the converter are connected to the information inputs of the reversible pulse counters 11, 12, 13 and the inputs of the input decoder zero 2 of the channel 1 selection node, the output of which is connected to the counting input of the binary pulse counter 3, whose outputs are connected to the inputs of the decoder. 4, the outputs of which are respectively connected to the recording inputs of the reversible pulse counters 11,12,14 of the corresponding channels B, 9,10, besides the last N-output of the decoder 4 is connected to the input of the NAND element 5, the second input of which is connected through the element NOT 6 with the reset input of the converter, and the output is connected to the reset input of the binary pulse counter 3, besides that the reset input of the converter is connected to the inputs of the resetting pulse counters 11, 12, 13, which are connected to the corresponding inputs Zero decoders zero 14,15,16, the outputs of which are connected to the inputs of the corresponding elements AND-NOT 20, 21, 22 and elements ILINE 17, 18, 19, and the second inputs of the elements AND-NOT 20 and IL AND-NOT 17 are connected to the output generator 7, the second inputs of the elements AND-NOT 21. 22 and OR-NOT 18, 19 are connected respectively to the outputs of the elements OR 26, 27, while the outputs of the elements OR-NOT 17, 18, 19 are connected to the subtractive inputs of the corresponding reversing pulse counters 11 , 12,13 and with the corresponding inputs of the element OR 29, the output of which is the output of the converter, and the outputs of the elements ENTs 20, 21, 22 are connected to the inputs of the corresponding elements OR 26, 27,28, the second inputs of which are connected to the outputs of the corresponding delay elements 23,24,25, the inputs of which are connected to the outputs of the reverse transfer of the corresponding reversing pulse counters 11,12 , 13.

Converter binary code in the number of pulse code works as follows.

When the power is turned on, the JI1, 12, 13 meters are reset along the reset line, as well as of the counter 3 via the NOT 6 element and the AND-NE element 5 to the initial zero state and the pulse generator 7 is turned on. The zero code on the decoder zero outputs 14,15 , 16 ensures that at their outputs there are signals prohibiting the elements OR-HE 17, 18, 19, thereby blocking the passage of the clock pulses of the generator 7 to the converter channels, as well as the signals opening the elements of the INE 20, 21, 22 to pass the clock pulses of the generator 7 on follow channel.

Convertible codes are fed to the input of the decoder zero 2 of the channel 1 selector node and to the inputs of the reversible counters 11, 12, 13. The decoder zero 2 detects the presence of a code and outputs a signal to the counting input of the needle pulses 3. A binary code is formed at the output of the meter corresponding to the code number Received on the binary code converter. In accordance with the binary code, at the outputs of the counter 3, at one of the outputs of the decoder 4, a signal is generated, which records the incoming code into the 5 reversible counter of one of the channels. The codes are recorded sequentially through the channels as they arrive at the converter. When a signal arrives at the N-ro converter from the N-ro output

0 decoder 4 is fed to the input of the record of the N-ro channel and to the NAND 5 element of the node 1 channel selection, forming at the output of the NAND 5 element a reset signal of the counter 3 to the zero state. After this (s + 1) -th code

5 will be recorded in 1st channel 8 of the converter.

The first code received by the converter is written to the reversible counter 11 of the first channel 8. The decoder is zero

0 14 captures the presence of a code and generates a signal, the locking element AND-NOT 20, blocking the passage of the generator 7 sync pulses to the next channel, and the OR-NOT 17 opening element. The sync pulses of the generator 7 through the open element OR-NOT 17 are fed to the counting input of the reversing counter 11 and through the element OR 29 to the output of the converter. Generator 7 sync pulses

0 reads the code written to counter 11 down to zero, and a number-pulse code is formed at the output of the converter, the number of pulses in which corresponds to the code to be converted. When the sync pulses subtract the code to zero at the output of the reverse transfer of the reversible counter 11, a signal is generated that includes a delay element 23, and a signal is received from the decoder zero 14

0 a locking element OR NOT 17, stopping the passage of the sync pulses of the generator 7 to the reversible counter 11, and the opening element AND-NOT 20. At the same time, the pulse signal is adjustable

6 of the duration comes from the output of the delay element 23 to the input of the OR 26 element, blocking the passage of the clock pulses of the generator 7 through the IL AND 26 element, and thereby forming a fixed pause between the generated number-pulse codes. Upon termination of the blocking pulse of the delay element 23, the element OR 26 is opened, the oscillator 7 clock pulses are passed to the inputs of the elements.

5 YLI-NE 18 and N-21 21 of the next channel 9. If the code to be converted is recorded in the reversible counter 12 of the second channel 9, the process of forming the number-pulse code of the second .rioro channel begins. The work of the second and the rest

Converter channels are similar to the first channel.

The technical advantage of the invention compared to the prototype is that, due to the introduction of a device for selecting channels and N channels for converting binary code into a number-pulse code, it is possible to significantly increase the rate of information input into the converter and also ensure that its input into the converter is independent of : to output due to the redistribution of incoming information using a channel selection device through binary code conversion channels followed by its successive transformation Azan, which significantly increases the speed of the device. The introduction of a delay element into a binary code conversion channel into a number-pulse code makes it possible to form an adjustable pause between the number-pulse codes at the output of the device, which eliminates the possibility of code overlapping and, therefore, obtaining a valid code.

Formulas a and 3 o bret and a binary code converter into a pulse number code containing a pulse generator and in the first information channel .- a reversible pulse counter, whose information outputs are connected to the inputs of the zero decoder, and the NAND element. the output of the pulse generator is connected to the first input of the NAND element, the information inputs and the reset input of the reversible counter are respectively the information inputs and the reset input of the converter, from which, in order to increase the reliability and speed of the converter, a multi-input element is introduced into it OR, information channel selection node, performed on the zero decoder, binary pulse counter, decoder, NOT element and AND-NOT element, the zero decoder output is connected to the counting

the input of a binary pulse counter, the outputs of which are connected to the inputs of the decoder, the output of the element is NOT connected to the first input of the NAND element, the output of which is connected to the reset input of the binary pulse counter, the output of the last digit of the decoder is connected to the second input of the AND-NOT element, the output of the element NOT is the reset input of the converter, the inputs of the zero decoder are connected to the information inputs of the converter, N-1 (N is the number of words to be converted) of information channels made similarly to the primary, and to each The IL channel, the delay element and the NO element, the first input of the OR information element of the first information channel are connected to the output of the pulse generator; in each information channel, the overflow output of the reversible pulse counter is connected to the first input of the element OR , the output of the OR element of each previous information channel, starting from the first, is connected to the first inputs of the OR-NOT element and the NE-NI element of the subsequent information channel, in each information channel e output of the zero decoder is connected to the second inputs of the input element OR NOT and the element NAND, the output of which is connected to the second input of the element OR, the output of the element OR NOT is connected to the subtractive input of the reversible pulse counter and the corresponding input of the multi-input element OR whose output and the output of the OR element of the last information channel are, respectively, the first and second outputs of the converter, the outputs of the decoder are connected to the recording inputs of the reversible pulse counters of the corresponding information ka als, data inputs and reset inputs of the reversible counter N-1 information channels Con cheny respectively to data inputs and a reset input of the converter.

Reset

Claims (1)

Formula Binary code-to-pulse code converter containing a pulse generator and in the first information channel 30 a reversible pulse counter, the information outputs of which are connected to the inputs of the decoder zero, and the NAND element, the output of the pulse generator is connected to the first input of the NAND element, the information inputs and the reset input of the reverse counter are respectively information inputs and the reset input of the converter, which means that, in order to increase 40 credibility and would of the converter’s performance, a multi-input OR element is introduced into it, an information channel selection node made on a zero decoder, a binary pulse counter, a decoder 45, an element NOT and an AND-NOT element, the output of the zero decoder is connected to the counting ⁸ input of the binary pulse counter, outputs which is connected to the inputs of the decoder, the output of the element is NOT connected to the first input of the AND-NOT element, the output of which is connected to the reset input of the binary pulse counter, the output of the last bit of the decoder is connected to the second input of the element It’s NAND, the output of the element is NOT a converter reset input, the inputs of the zero decoder are connected to the information inputs of the converter, N-1 (N is the number of words to be converted) of information channels made similar to the first, and the OR element is additionally introduced into each information channel,, delay element and OR-HE element, the first input of the OR-NOT element of the first information channel is connected to the output of the pulse generator, in each information channel the overflow output of the reverse pulse counter through the element LCD is connected to the first input of the OR element, the output of the OR element of each previous information channel, starting from the first, is connected to the first inputs of the OR-HE element and the NAND element of the subsequent information channel, in each information channel the output of the zero decoder is connected to the second inputs of the inputs of the element OR-HE and the AND-NOT element, the output of which is connected to the second input of the OR element, the output of the OR-HE element is connected to the subtracting input of the reverse pulse counter and to the corresponding input of the multi-input OR element, the output to The second and the output of the OR element of the last information channel are respectively the first and second outputs of the converter, the decoder outputs are connected to the recording inputs of the reverse pulse counters of the corresponding information channels, the information inputs and the reset inputs of the reverse counters N-1 of the information channels are connected respectively to the information inputs and the reset input of the converter .