SU1677856A1 - Pulse length discriminator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices and systems for automation, telemechanics and data collection. Pulse selector by duration contains shaper 1 pulses, elements AND 2. 8 and 13, input bus 3, delay element 4, counters 5 and 9 pulses, element NOT 6. trigger 7, element OR 10, decoder 11. generator of 12 pulses, output bus 14. Eliminating the possibility of the formation of a shortened pulse on the output bus when an input pulse overlaps in time with a previous input pulse restored on the output bus allows increasing the device speed while increasing the reliability of lectures. 2 Il.

Description

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The invention relates to a pulse technique and can be used in devices and systems for automation, telemechanics and data collection.

The purpose of the invention is to increase the speed of the device while at the same time increasing the reliability of selection by eliminating the possibility of forming a shortened pulse on the output bus when an input pulse overlaps in time with the previous input pulse restored on the output bus.

FIG. 1 shows a structural electrical selector circuit; in fig. 2 - time diagrams that show his work.

The device (figure 1) contains a driver 1 pulses, the input of which is connected to the second input of the first element 2 and the input bus 3, and the output - to the input of the delay element 4, the output of which is connected to the reset input of the first pulse counter 5, the first element 6 , trigger 7. The output of the delay element 4 is connected to the C-input of the trigger 7 and the first input of the second element AND 8, the output of which is connected to the recording input of the second counter 9 pulses, and the second input - with the output of the element OR 10 whose inputs are connected to the corresponding outputs descrambler 11. Tre The second input element And 2 is connected to the output of the pulse generator 12 and to the first input of the third element And 13. The borrowing output of the counter 9 is connected to the output bus 14, to the second input of the And 13 element and to the input of the HE element 6. The output of the delay element 4 is through the second element NOT 15 is connected to the second input of the fourth element AND 16, the first input of which is connected to the output of the element 6, and the output to the R input of the trigger 7, the inverse output of which is connected to the third input of the element 8. The first input of the element 2 is connected to the output counter overflows 5, and the output - with summing input of the counter 5, whose outputs are connected bitwise with the inputs of the decoder 11 and also with porazr dno- counter data inputs 9, a subtracting input connected to the output of AND gate 13.

The selector works as follows.

In the initial state, the outputs of counter 5 are zero signals, the transfer output is a single signal, the output of counter 9 and the output bus 14 is a zero signal, and the output of trigger 7 is a single signal.

When a pulse appears on the input bus 3 (Fig. 2a), the element And 2 opens and the pulses from the generator 12 (Fig. 2b) begin to flow to the summing input of the counter 5 (Fig. 2c). Converting the duration of the input pulse in the code of the number of pulses of the generator 12.

In this case, if the duration of the input pulse is longer than the minimum permissible limit set by the decoder 11, then the outputs of the decoder 11, and therefore, at the output of the OR 10 element and at the second input of the AND 8 element, single signals will appear (Fig. 2c, d in this

In 5 cases, the decryptor 11 sets the limits 3-4, 7-8, 10-11). These single signals will not pass to the output element And 8, since there is no enabling pulse from the element 4 delay

0 (figg, d, e).

At the moment of the end of the pulse on the input bus, the driver 1 emits a pulse which appears after the time t at the output of the delay element 4, at the C input of the trigger 7, at the input of the element HE 15 and the first input of the element 8. If the duration of the input pulse was in one of the established limits, this impulse will pass through the element AND 8 to the input of the record

0 of counter 9 (FIG. 2e) and on the leading edge will write the code from the outputs of counter 5 to counter 9. At the output of the counter 9 and on the output bus 14, a single signal appears that opens the element And 13 and inverts on the element NOT 6, closes the element AND 16. On the output bus 14, the reproduction of the received input pulse starts (Fig. 2g). On the falling edge of the pulse from the output of the delay element 4, the counter 5 is set to its initial state, the output of the trigger 7 is set to a zero signal (Fig.2i), which goes to the third input of the element 8 and prohibits the formation of the information recording signal in

5 counter 9 from counter 5 for the entire duration of the reproduction of the received pulse. From this point on, the reception of the next input pulse is allowed.

Through the element And 13, the pulses of the generator 1 begin to flow to the subtracting input of counter 9, i.e. the pulse duration is tested. At the moment of termination at the subtractive input of the counter 9, the pulse that wrote down the number 9 in the counter 9,

5, the single signal at the exit of the loan of counter 9 disappears, and the element 13 is closed, i.e. the reproduction of the received pulse on the output bus 14 (fig.2h, h) ends. The zero signal from the output bus 14, inverting on the element NOT 6, opens the element AND 16 and, if there is no single pulse at the output of the element 4 of the delay 4, zeroes the trigger 7, sets it to its initial state. If, during reproduction of the received pulse on the output bus 14, the next pulse was received from the input bus 3, then after the end of its reception, the cycle of the device will repeat as described above.

If, after the end of the input signal, its duration does not match any of the set limits of the decoder 11, then at the output of the element OR 10 and at the second input of the element And 8 there will be no allowing single sip-ala. Therefore, the pulse issued by the former 1 at the end of the input pulse and through time r received by the output of the delay element 4 and the first input of the AND 8 element does not pass to the output of the AND 8 element. Therefore, there will be no overwriting of the information from counter 5 to counter 9, counter 9 will not change its state, and a zero signal will remain on the output bus 14. On the falling edge of the pulse from the output of the delay element 4, the counter 5 is reset to its original state and the device is ready to receive the next input pulse.

If the duration of the input pulse on bus 3 exceeds the maximum value of the code that can be written to counter 5, the last one is filled completely and at the moment of the end at the summing input of the pulse that has written the number 11 ... 1 to counter 5, its output transfer There is a zero signal that closes the element AND 2. Therefore, before the end of the input pulse to the summing input of the counter 5, the pulses from the generator 12 will not be received. After the pulse at the input bus 3 terminates at the falling edge of the pulse from the output of the delay element 4, the counter 5 is zeroed and the device is ready to receive the next input pulse. On the output bus 14, the pulse is not reproduced.

Thus, the selector has an increased speed when receiving and playing controlled pulses,

and also excludes the possibility of reproduction of the pulse shortened in comparison with the input

Claims (1)

Claims of the pulse duration selector comprising the first element I, the first input of which is connected to the overflow output of the first pulse counter, the second input to the input of the pulse former, the third input to the output of the pulse generator, and the output to the summing input of the first pulse counter, input the reset of which is connected to the first input of the second element I and through the delay element to the output of the pulse former, and the outputs are bitwise connected to the information inputs of the second pulse counter and the inputs of the decoder The corresponding outputs of which are bitwise connected to the inputs of the OR element, the output of which is connected to the second input of the second element AND, the output of which is connected to the recording input of the second pulse counter, the subtracting input of which is connected to the output of the third element And, the first input of which is connected to the output of the pulse generator and the second input - With the output bus, the output of the loan of the second pulse counter, and through the first element NOT with the first input of the fourth element I, as well as the input bus, characterized in that, in order to increase the speed operation of the device while simultaneously improving the reliability of the selection by eliminating the possibility of forming a shortened pulse on the output bus when an input pulse overlaps in time with the previous input pulse restored on the output bus, a trigger and a second element HE are inputted, which is connected to the output of the delay element and with the C input of the trigger, and the output with the second input of the fourth element I, the output of which is connected to the R input of the trigger, the inverse output of which is connected to tert their entrance the second AND gate, the pulse shaper input coupled to the input bus.