SU1272490A1 - Device for selecting the first and the last pulses in pulse burst - Google Patents

Abstract

The invention can be used in telemechanics, measurement and automatic control systems. The purpose of the invention is to increase reliability. The device contains a generator of 1 pulses, D-triggers 5 and 6 to the elements And 7 and 8. The introduction of registers 2 and 4 of the shift and the formation of new functions with links ensures a reliable selection of the first and last pulses of the packet under study and the number of pulses in which is unknown, regardless of pulses and pauses between pulses in packs. At the same time, possible malfunctions in the operation of the device are eliminated: losses of the first or several first impulses of a pack of 2 sludge.

Description

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Fig. 1 I The invention relates to a pulse technique and can be used and automatically controlled.

The purpose of the invention is to increase reliability by eliminating the possibility of skipping the first or several first pulses in a packet.

FIG. 1 shows the electrical functional scheme of the device; 2, time diagrams of the device operation.

The selection device of the first and last pulses in the packet contains a pulse generator 1, the output of which is connected to the clock input of the first shift register 2, whose information input is connected to the input bus 3 and the right shift input of the second shift register 4, the first output - to the left shift input of the second register 4 shifts and Svhodami first and second D-triggervr 5 and 6, the second output - with the first inputs of elements And 7 and 8, Schlokhod first element And 7 connected to the first output bus 9, and the second input - to the output of the second D trigger 6, whose input connected to the second input element And 8 and the inverse Output of the first D-flip-flop 5 whose D-input is connected to the output of the second shift register 4, the output of the second element And 8 is connected to the second output bus 10.

The device works as follows.

In the initial state, from the output of D-flip-flop 5, a high potential (log. 1) is fed to the second input of element 8 and to the D-input of D-flip-flop 6, from the output of which low potential (log. O) goes to the second input of element I 7

The contents of all the cells of registers 2 and 4 of the shift is zero (Fig. 2 c, d, d, g, i, k). The length of shift register 2 is equal to (N + I) cell, and the first and second outputs of shift register 2 are its outputs (AND + O th and N-th corresponding cells.

Pulse trains arriving at the input bus 3 (fig. 2 b) are sent to the D input of the shift register 2 and the clock pulses of the generator 1 (FIG 2 a) arrive at the input of the shift register 2, are recorded and shifted in it forward direction.

shift to the input right, recording and shift of the signal log.

in the forward direction (Fig. 2, k), and on the leading edge of the pulses from the N-output of the shift register 2 (Fig. 2 to act on the shift input to the left of the shift register 4, the signal and the log. O the opposite direction. The output of the shift register 4 is the output of its second cell (Fig. 2k).

Let dT be the known minimum interval between the front edges of neighboring pulses belonging to different packs. Then, with adjacent pulses, the input to the device, belong to the same bundle, and when - to different bundles.

The length of the shift register 2 is chosen according to the formula, where f is the pulse frequency of the generator 1 N - the minimum number of cells in the register.

The time interval L between the leading edges of adjacent pulses in shift register 2 is measured by the number of cells n of this register, which are located between cells, corresponding to the leading edges of neighboring pulses. Then, with shift 2 in register 2, there are pulses belonging to the same pack, and with - pulses of different packs.

The verification of the implementation of these inequalities is carried out in shift register 4. When in shift register 2, no more than one pulse is found, and with not less than two pulses, i.e. The control over the implementation of these inequalities is carried out according to the state of the second check register 4. When in register 4 of shift, the code is 1000., .O, which means O is written in its second cell, When the minimal code looks like 11000, .O, t, e, 1 is written in the second cell,

Claims (1)

Thus, the sdving register 4 captures the number of incoming pulses in shift register 2 in a single linear code, as the pulse entering into shift register 2 adds one to the linear one code, and the output output pulse deducts it. 1272490 In shift register 4, which is reversible, on the leading edge of the fiA4 & K input pulses, step by step. The first and all following burst pulses, arriving at the device input, are recorded and shifted at frequency f in shift register 2. At the same time on their leading fronts in the register 4 shift occurs, respectively, the recording and shift of the signals log. 1, i.e. appendix 1 to linear unit code. The first burst of a burst appears at the second output of the shift register 2 through time. At this point, in the shift register A, a linear unit code is formed with the number of units m equal to the number of pulses arriving at the input of the device during time t. Since, at the time of the appearance of the leading edge of the first pulse at the second output of shift register 2, a log is present at the output of shift register 4. 1, arriving at the D-input of the D-flip-flop 5. With the appearance of the leading edge of the first impulse of the stack at the output N of the shift register 2, the trigger 5 is set to one state, in which the signal log goes from its output to the input of the element And 8 . Oh, prevent the pulses from passing to the output bus 10 of the devices (Fig. 2 l). On this heh front, the D-flip-flop 6 is set to a single state, and a log is sent from its jupsode to the second input of the output point 7. 1, and in the sdving register 4, the I is subtracted from the unit line code (Fig. 2m). In the next cycle, the first burst of the packet is shifted by one cell and appears at the (N + 1) -M output of the shift register 2, where through open element 7 and passes to the output bus width 9 of the device (ftn. 2n). Upon the arrival of the leading edge of the second pulse of the packet, the N-output of the shift register 2, trigger 6, returns to the zero state, since its D-input from D-trigger 5 receives a log signal. A. At the same time, from the output of Dtrigger 6 and the second input of the element: And 7 a signal is received. O, preventing the passage of the remaining pulses of the stack and the output bus 9 of the device. At the same time, the same substitution in register 4 of the shift results in a queue subtraction of 1 of the third, third-party code. 904 When the front edge of the second input pulse arrives at the input of the shift register 4 at its output, the signal log is. Regardless of the change in code in shift register 4, it remains until the last-to-last burst of the packet appears at the N-output of shift register 2. With the appearance of the penultimate impulse of the packet at the N-output of the shift register 2, a log appears in the output of the shift register by 1 unit linear code in the shift register 4. A. Before the arrival of the last pulse of the stack, the log levels of the D-flip-flop outputs 5 and 6 are maintained. A. Upon the arrival of the leading edge of the last pulse of the packet to the N-output of the shift register 2, the D-flip-flop 5 returns to its original, zero, state and from its output to the second input of the And 8 element a log is received. 1, allowing the passage of a pulse to the output bus 10 (FIG. 2 p). In the next clock cycles, the last pulse of the stack, moving in shift register 2, appears at its N + 1 position, from where it passes through the open element of the PI to the output bus 10 of the device. In this case, the output of the b-flip-flop 5 remains log. I, the incoming second input element And 8 and the input of the D-flip-flop 6, and the device is ready for the next cycle. Thus, the proposed device provides a reliable selection of the first and last pulses of the investigated pack, the number of pulses in which is unknown, regardless of the duration and; pulses and pauses between pulses in packs. At the same time, possible malfunctions in the operation of the device are eliminated: losses of the first or several first impulses of the stack. The invention The first and last pulse extraction device in a pack containing a pulse generator, input one, two output buses, first of which is connected to the output of the first lemeite And, the first input of which is connected to the output of the first trigger, second trigger, which output is connected to the first input The second element, And, is different; in order to increase reliability, two shift registers are entered into it, the first input of the first of which is connected to the output of the pulse generator, the second input to the input bus and the first input of the second p Header of the shift, the first output - with the second inputs of the elements And, the second output - with the first input of the first trigger 1224246 gera, the first input of the second trigger and the second input of the second shift register, the output of which is connected to the second input of the second trigger, the output of which is connected to the second input of the first trigger, the output of the second element And is connected to the second output bus. but FIG. 2