SU734662A1 - Information receiving device - Google Patents

Description

The invention relates to computing and is intended to receive commands received over a communication channel in a serial code.

A device for receiving information containing AND, OR, NOT, triggers, a synchronization unit, the output of which is connected to the first input of the AND element, and a serial code converter, including a shift register, decipher and counter 1, are known.

However, this device is not operational, but in the case when the command pulses coming through the communication channel are not synchronous with the internal frequency of the device.

The closest in technical essence to the invention is a device comprising a synchronization unit, the output of which is connected to the first input of the frequency lock unit, the second input of which is the switching input of the device, a switch connected to the first input of the AND element, the output of which is connected to 20 reception gistrom, storage unit, delay elements, analyzer, driver of control signals, multiplexer, confirmation signal conversion unit, message conversion units, message selection, selection Mode, the register 2 messages.

Known devices have low reliability when receiving information, because they do not provide protection as a 6m reception of a false command; as well as from interference occurring in the communication channel, due to the fact that it is not possible to reset a received command, in which the number of bits is less than a given one, as a result of it, false information can accumulate in the device, resetting the received command, in which any impulse disappears For example, due to the influence of interference in the communication channel, as well as the received command, in which a false pulse appears, which also occurs, for example, under the influence of interference in the communication channel.

The purpose of the invention is to increase the reliability of the pa6oTbi device.

The goal is achieved by the fact that a device containing a synchronization unit, the output of which is connected to the first input of the element AND and the first input of the driver of control signals, the second input of which is connected to the input of the device, and a serial code converter.

the first input of which is connected to the first output of the control signal generator, the output is connected to the device output, the received information monitoring unit, the frequency setting unit, the counter, the trigger and two OR elements are entered, and the second control signal generator output is connected to the first input of the first OR element , the second input of which is connected to the first output of the driver of control signals, and the output is connected to the first inputs of the control unit of the received information and the counter, the second input of which is connected to the output And the output of the counter, through the frequency setting block, is connected to the second inputs of the serial code converter and the control unit of the received information, the output of which is connected to the third input of the serial code converter and the first input of the second OR element, the second input of which is connected to the output of the serial code converter, output the second element OR is connected to the zero input of the trigger, the single input of which is connected to the third output of the control driver, the single output The trigger is connected to the second input of the AND element and the third input of the control unit of the received information. In addition, the control unit of the received information contains a control counter, a delay element, elements AND and OR, the first input of the control counter through the delay element connected to the first input of the block and the first input of the AND element, the second input of which is connected to the third input of the block, the third input connected to the first output of the control counter, the second input of which is connected to the second input of the block, and the second output connected to the first input of the OR element, the second input of which is connected to the output of the AND element, the output connected to the output of the block; The frequency setting unit contains a switching field, a decipher and a comparison node, the output of the switching field is connected to the first input of the comparison node, the second input of which is connected to the block input through the descrambler and the output of the comparison node is connected to the output of the block.

The drawing shows a functional diagram of the device.

The device contains a synchronization unit 1, the output of which is connected to the first inputs of the AND 2 element and the driver 3 of the control signals, the second input of which is connected to the input of the device 4, and the first output is connected to the first input of the serial code converter 5 and the input of the first OR 6 element, output through which the counter 7, the frequency setting block 8 and the control block 9 of the received information are connected to the first input of the second element OR 10, the second input of which is connected to the output of the device AND, the output is connected to the zero input of three Gera 12.

Unit 9 of the control of the received information contains the counter 13 of the control, the outputs of which are connected to the element AND 14 and the element OR 15, the element 16 delay.

The frequency setting unit 8 comprises a switching field 7, the output of which is connected to the input of the comparison node 18, the other input of which is connected to the output of the decipheror 19.

The Converter 5 of the serial code contains the switch 20 reception, the first output of which through the element 21 is connected to the register 22, and the second output is connected to the element 23 of the delay.

The device works as follows.

Before starting, the counter 7, trigger 12, memory elements, containing in the control signal e 3 control signals of the serial code converter 5, the control information block 9, are set to zero (initial) state (the circuit of the installation of memory elements in the drawing not shown).

The device begins to operate from the moment a command arrives at input 4. Each command is a binary one, of a required duration, a code combination (codogram) with a polar sign, where one polarity is taken as an information unit, and the other is zero.

The serial code command comes from the input 4 to the second input of the driver 3 control signals. Shaper 3 control signals are designed to bind incoming command pulses to the internal frequency of the device, as well as to generate code and clock pulses and to generate a "pulse received" signal. When receiving each positive command pulse, the shaper 3 control signals generates a " the code pulse at the first output, which corresponds to the reception of “a unit of information. When each pulse of the negative polarity command is received, the driver of the control signals generates a signal "clock pulse at the second output, which corresponds to the reception of zero information. The pulse signal received by the driver of the control signal 3 generates at the third output each time after issuing either a clock pulse or a code one.

Consider the operation of the device in the case where the command consists of eight bits, the first bit of the command being an impulse, for example, positive polarity. After analyzing the first pulse, the ksmandi shaper 3 control signals generates at the first you run a code pulse that goes to the first input of the serial code converter 5 and to the second input of the first element OR 6. Serial code converter 5 is designed to convert the serial command code to parallel code . When the first command pulse arrives, the receive switch 20 is in the zero state and produces at the first output a signal that opens the AND 21 element so that the first "code pulse is recorded into the first register bit 22. At the same time, the" code pulse through the OR 6 element sets counter 7 and counter 13 of the control to zero (the initial state and opens element 14 of the first input. However, element 14 does not work, because there is no enable signal at its second output coming from single output three 12. After the end of the code pulse, the control signal generator 3 generates at the third output a signal "pulse received, which sets trigger 12 into one state. Signal from single output of trigger 12 opens elements 2 and 14 on the second input. After that, pulses from the output of the synchronization unit 1 through the element I 2 begin to flow to the second (counting) input of the counter 7, transferring it sequentially from one state to another. Each state of counter 7 is analyzed in frequency setting block 8. Using the frequency setting block 8 and the counter 7, a waiting time interval is set; the arrival of the next impulse command. The extremes of this time interval are calculated as follows. The accuracy of the measurement of the time interval depends on the internal frequency of the device, i.e. on the pulse frequency from the output of the synchronization unit 1. In this case, it is necessary that the internal frequency of the device is greater than the pulse frequency of the command. The frequency setting unit 8, based on the analysis of the state of the counter 7, generates signals at times corresponding to the minimum and maximum waiting times for the next command pulse. Since, depending on the internal frequency of the device, the pulse frequency of the command 1B and the accuracy of setting the timeout interval, the values change, for universality, the state of the counter 7 is set using a switching field 17. The switching field 17 can be arranged using switches or a switchboard. jumpers, or in such a way that from its output two numbers arrive at the first input of the comparison node 18. To the second input of the comparison node 18, the position code of the counter 7 arrives from the output of the decimator 19. The comparison node 18 generates an output signal only when the state of the counter 7 is equal to one of the numbers set in the switching field 17. In the considered case, after as the counter 7 is set to the fourth position, a signal is output at the output of the comparison unit 18. This signal sets the reception switch 20 to the first position at which the element 21 21 opens so that the second command pulse is recorded in the second register bit 22. At the same time, the signal from the output of the comparison node 18 sets the control counter 13 to the next first position. After that, the signal from the first output of the monitor 13, corresponding to the zero state of the monitor 13, is removed, and the device is ready to receive the next, second command pulse. If there is no distortion in the communication line, then the next pulse enters the device via input 4 at a specified cooling time interval. Suppose the second command pulse has a negative polarity. In this case, the driver 3 of the control signals generates a signal at the second output. This signal through the first element OR 6 sets the counter 7 to the initial, zero position. In addition, this signal is fed to the input of the delay element 16 and to the first input of the And 14 element. However, the And 14 element does not work, since at its third input there is no enable signal from the first output of the control meter 13. After the time required to perform the operations described above, the effect of the signal at the second output of the driver 3 of the control signals is completed. Only after this does the signal appear at the output of the delay element 16, which sets the control counter 13 to the initial, zero state. At the same time, after the synchronizing pulse has ended, the control signal generator 3 generates a pulse signal received at the third output, which confirms the single state of trigger 12. This completes the reception of the negative polarity command pulse and does not record any information in the next register register 22, and it remains in the zero state, which corresponds to the reception of zero information. After receiving the next, second pulse command, as described above, the counter 7 begins to count the pulses coming from the output of the synchronization unit 1. When the counter 7 is set to the fourth state, corresponding to a time stamp equal to the minimum time, the comparison node 18 is triggered. According to the signal from the output of the comparison node 18, the receive switch 20 goes to an alternate, second position, in which the element 21 is opened so that the third command pulse is written to the third bit of the register 22. In addition, the output signal from the comparison node 18 goes to the second input counter 13 control, set it to the first state. After that, the device is ready to receive the next command pulse. The reception of successive command pulses is carried out as described above.

After receiving the latter, in the considered case of the eighth pulse of the command, the receive switch 20 is set to the initial zero state by a signal from the output of the comparison node 18 and generates a signal at the second output. This signal arrives at output 11 and can be used to organize the reading of a parallel code of a received command from register 22 to a RAM. At the same time, the signal from the second output of the receive switch 20 through the second element OR 10 sets the trigger .12 to the initial zero state. As a result, the resolution signal is removed, arriving at AND 2 and 14. After the time required to perform the above operations, a signal appears at the output of delay element 23, which sets the register 22 to the initial, zero state. After that, the device is ready to receive the next command.

Consider the operation of the device in case of receiving a false command in which the number of bits is less than the specified one.

As an example, let us consider the case when a command consisting of only seven bits (pulses), instead of a given command of eight bits, arrived at the device.

In this case, all command pulses entering the device as described above are analyzed and recorded in register 22. After receiving the seventh command pulse, counter 7 and control counter 13 are set to zero and counter 7 starts counting the pulses from the output of synchronization unit 1 again. . When the counter 7 is set to the fourth state, the comparison node 18 is triggered. By the signal from the output of the comparison node 18, the receive switch 20 moves to the next, seventh position, in which the element 21 opens so that the eighth command pulse is recorded in the eighth register bit 22. In addition, the output signal of the comparison node 18 goes to the second input of the counter 13 controls, setting it to the first position. Since the eighth command impulse is absent, during the entire waiting time of the next command impulse, the shaper 3 control signals do not generate any signals.

Therefore, the counter 7 is set to the generic state. Since the first input of node 18 is compared with the output of the switching floor

17, the position code corresponding to the sixth state of the counter 7 is received, then the comparison node 18 again produces an output signal. The signal from the output of the comparator node 18 arrives at the receive switch 20, putting it into the next state.

In addition, according to the signal from the output of the comparison node 18, the monitor counter 13 is set to the zero state and generates a signal at the second output. This signal through the element OR 15 sets the reception switch 20 to the initial, zero state and resets the information recorded in register 22. At the same time, the signal from the second output of the control meter 13 through the elements OR 15 and 10 sets the trigger 12 to the initial, zero state. After that, the device is ready to receive the next command.

Thus, the device resets a false command, in which the number of bits is less than the specified one, as a result of which it is protected from receiving false information.

Consider the operation of the device in the case of receiving a command in which, due to the effect of interference, there is no fourth command impulse in the communication channel.

In this case, the first three command pulses entering the device, as described above, are analyzed and recorded in register 22. After receiving the third command pulse, the comparison node 18 is triggered, the output of which sets the receive switch 20 to the next third state.

Simultaneously. On the signal from the output of the comparison node 18, the counter 13 is set to the first state. Since the fourth command pulse is absent, during the entire time of waiting for the next pulse of the command, the driver 3 of the control signals does not generate any signals. Therefore, after the maximum waiting time, as well as in the case of receiving a false command, the comparison node 18 generates a second control signal. According to this signal, the counter 13 of the control goes to the zero state and generates a signal at the second output, which through the element OR 15 sets the receive switch 20 and the register 22 to the initial, zero state. At the same time, the signal from the second output of the counter 13 through the elements OR 15 and 10 sets the trigger 12 also to the zero state.

Claims (1)

The next, fifth command pulse is evaluated by the device as the first pulse of a new command. Therefore, the remaining command pulses, i.e., pulses from the fifth to the eighth, are received and analyzed in the same way as described above, yo are recorded in this case, respectively, in the first four bits of register 22. After receiving the last, eighth command pulse, after a time, the minimum wait time , the comparison node 18 is triggered, the output of which sets the reception switch 20 to the next, fourth state. Therefore, in the considered case, after receiving the last, eighth pulse, the switch 20 does not produce a signal at the second output. At the same time, the signal from the output of the comparison node 18 compares the control counter 13 to the first stage. Since no information is received by the input 4 into the device, the control driver 3 produces no output signals. Therefore, after maximum waiting time, the comparison node 18 re-generates the output signal. By this signal, similarly to the above, the receive switch 20, the register 22, the trigger 12 and the control counter 13 are reset, after which the device is ready to receive a new command. Thus, the device provides a reset of the received command, in which any impulse is lost due to interference in the communication channel. Consider the operation of the device s in the case of receiving a command in which a false pulse arises under the influence of interference in the communication channel, for example, between the second and third impulse of the received command. In this case, the first two pulse commands entering the device are analyzed and recorded in register 22 in the same way as described above. After receiving the second pulse, the counter 7 starts counting the pulses from the trigger and the synchronization unit 1. If, at input 4, a device receives interference, which is identified as a pulse, for example, "single information," the driver 3 of the control signals generates a signal at the first output. This signal sets counter 7 to the zero state and arrives at element 14. Since the disturbance occurred before the minimum waiting time, the control counter 13 is in the zero state and produces a signal at the first output, which opens element 14 at the third input . Therefore, the signal from the first output of the driver 3 of the control signals triggers the element And 14. The signal from the output of the element 14 through the element 15 sets the receive switch 20 and the register 22 to the original, zero state. At the same time, the trigger 12 is also set to the zero state. The remaining six command pulses are received by the device as described above. After receiving the last command pulse, the received information monitoring unit 9 re-generates an output signal that resets the information recorded in register 22 and returns the receive switch 20 and the trigger 12 to its original state. Thus, the device clears the received command in which spurious pulse arising from interference in the communication channel. The use of the considered device, in comparison with the known devices, provides an increase in the reliability of the reception of information, since protection is achieved both from the reception of a false command and from interference in the communication channel. due to the fact that the device provides a false command reset, in which the number of bits is less than the specified one, as a result of which protection against receiving false information is achieved, the received command is reset. in which any impulse disappears, for example, due to the effect of interference in the communication channel, a reset of the received command, in which a spurious impulse occurs, which also occurs, for example, under the influence of interference in the communication channel. Claims I. An apparatus for receiving information comprising a synchronization unit, the output of which is connected to the first input of the element AND and the first input of the driver of control signals, the second input of which is connected to the input of the device, and a serial code converter, the first input of which is connected to the first output of the driver control signals, the output is connected to the output of the device, characterized in that, in order to increase the reliability of operation, a block of control of the received information is entered into it, the counter, trigger and two OR elements, the second output of the control signal generator is connected to the first input of the first OR element, the second input of which is connected to the first output of the control signal generator, and the output is connected to the first inputs of the control unit of the received information and the counter, the second input of which is connected to the output of the voltage I, the output of the counter through the frequency setting block is connected to the second inputs of the serial code converter and the control block of the received information, the output of which is Connected to the third input of the serial code converter and the first input of the second OR element, the second input of which is connected to the output of the serial code converter, the output of the second element OR is connected to the zero input of the trigger, the single input of which is connected to the third output of the driver of the control signal, the single output of the trigger is connected to the second input of the element And to the third input of the control unit of the received information.