SU1280423A1 - Device for compressing and transmitting the telemetring information - Google Patents

Description

(21) 3919577 / 24-24

(22) 07/02/85

(46) 12/30/86. Bul IP 48

(72) I.V. Litovchenko, A.V. Petrushko

and V.A. Resnick

(53) 621.398 (088.8)

(56) USSR author's certificate 1005147, cl. G 08 C 18/28, 1981. USSR Copyright Certificate No. 1123045, cl. G 08 C 19/28, 1983.

(54) DEVICE FOR COMPRESSION AND TRANSMISSION OF TELEMETRIC INFORMATION

(57) The invention relates to an information-measuring technique and

can be used in systems for collecting and transmitting information, in particular in telemetry systems. The invention makes it possible to increase the information content by changing the sampling frequency of the sensors depending on the activity of the parameters. The device contains a switch, an analog-to-digital converter control unit, AND elements, a channel number counter, comparison units, a memory unit, a counter with initial setting, a read unit, a delay element. The control unit is implemented on a register, frequency divider, trigger, AND, OR, 1 hp elements. f-ly, 3 ill. The invention relates to information and measuring technology and can be used in systems for collecting conversion and transmission of information, in particular in telemetry systems. The purpose of the invention is to increase the information content of the device due to the nodes of the change in the sampling frequency of the sensors, depending on the activity of the input parameters. FIG. 1 shows a block diagram of the device in FIG. 2 is a control block diagram of FIG. 3 shows timing diagrams explaining the operation of the control unit. The device for compressing and transmitting telemetry information contains (FIG. 1) switch 1, control unit 2, synchronizer 3, AND 4 element, channel number 5, analog-to-digital converter 6, comparison block 7, memory block 8, block 9 match, counter 10 with the initial setting, the comparison unit 11, the AND element 12 and the delay element 13. The control unit 2 contains (Fig. OR 14, trigger 15, OR 16, AND 17 elements, frequency divider 18, shift register 19 and AND 20 element. Block 2 polls the channels specified by the external device, synchronizes the device operation together with synchronizer 3 developed on the basis of nodes made on integrated circuits of the 564 series. Counter 10 with the initial installation is a binary counter with the initial installation performed on the integrated circuits of the 564. The device works as follows. The number of channels that are most active at a given time is inputted to the information inputs of the switch 1. The second control input to the external device control unit 2 includes the sequence of pulses with a high the frequency is fed to the input of the counter of 5 numbered channels, until the output of the counter of 5 channel numbers does not match the channel number to be polled. At the same time, from the second output of the control unit 2, a permitting signal is output to the first input of the AND 4 element and the number of the channel to be polled, to the control input of the switch 1, to the second (address) input of the memory block 8 and to the second (addressable) input block 9 readout. Switch 1 connects the selected channel to the input of analog-to-digital converter 6, which converts the analog signal into a binary code. The parallel code of the input signal is compared in block 7 of the comparison with the code of the previous informative coordinate of the given channel at the given address, which is located on the block of memory 8. If the coordinate value of the input signal does not differ from the value of the previous coordinate, i.e. the coordinate is redundant, the comparison block 7 does not work, the coordinate is not written to the read block and the control block 2 selects the next predetermined channel. If the coordinate of the input signal differs from the value of the previous coordinate by an amount exceeding the response threshold of the comparison block 7, i.e. the coordinate is informative, the comparison block 7 outputs a signal to the And 12 element, allowing the coordinate to be written to the reading block 9, in block 8 of the memory at the corresponding address and on the counter 10c by the initial setting, increasing the content by one. In comparison block 11, the contents of the counter 10 are compared with the initial installation and the counter 5 of the channel numbers. If the natural order of the channel following is not violated, then the comparison unit 11 generates a signal that turns off the address bits in the readout block 9, and if the order of the channels is violated, then the address of this informative coordinate from the output of the And 4 element is recorded in block 9. The signal from the output of the comparator unit 11, passage through the delay element 20, informs the external device that a new significant sample is contained in the reader unit 9. According to this signal, the external device reads out the essential coordinate from the reading block 9. The control unit 2 operates as follows. The sequence of pulses from the synchronizer 3 is fed to the input of the control unit 2 and then to the input of the element AND 17 and to the input of the divider 18. In the initial state, the trigger 15. set to the zero state, locking the element AND 20, the third input of the control unit 2 contains the level O, which prohibits the operation of the divider 18. The same level O, entering the input of the counter 5 channel numbers, sets it to zero. On the second control input of the control unit 2, the parallel code register 19 registers the channels that need to be interrogated at the given moment. The presence of O in any cell of register 19 indicates that the channel corresponding to this cell is subject to interrogation. A signal is written to the input of control unit I from an external device. A record is written in the form of level 1, which unlocks the AND 17 element and enables the divider to operate. The same level 1, entering the second input of the counter 5 channel numbers, enables the counting. Since the first input of the element OR 16 from the output of trigger 15 is applied to the level O, the state of the output of the element OR 16 repeats the state of the output of the register 19. Since the output of the element OR 16 is connected to the second input of the element AND 17, the pulses arriving at the third input of control unit 2 and, later, the third input of element 17, passes to the first input of register 19 and shifts its contents until level O is reached at the output of register 19. Simultaneously, pulses blunt on the first output of the control block 2 and further on the first so Marketing input of the counter 5 channel numbers. Thus, the channel number counter 5 is set to the state corresponding to the channel number that is to be polled first. The impulse from deli / el 18, arriving at the second output of control unit 2, unlocks element 4 and allows passage of the generated channel address from counter 5, channel numbers through element 4 to the control input of the switch. Next, the appropriate channel is selected, the analog signal is converted to a digital code, a test for materiality, to be followed and recorded if the coordinate is significant. Cutoff pulse from divider 18 through OR 14 trigger 16 switches to state 1. This level 1, passing through the OR 16 element, hits the first input of the AND 17 element and allows the next pulse to be transmitted from the synchronizer to the register input 19. Through the cut off of this the pulse of the register 19 is shifted by one position, the trigger 15 through the elements AND 20 and OR 14 again switches to zero and the channel number counter 5 increases its contents by one. Now, if the output of the shift register 19 is zero again, i.e. the next channel is also to be polled, then control block 2 goes into standby mode before the next pulse arrives from the output of divider 18. If further in the cells of register 19 one or more units are contained, i.e. this row of channels is not polled, they are skipped in the manner described. The output of register 19 is connected to its second input, which turns it into a circular shift register. This allows you to repeatedly poll a selected group of sensors. If it is necessary to add or exclude from the survey part of the sensors, the third input of control unit 2 is supplied with level O, a new group of sensors is recorded in register 19, and level 1 is again set at the third input of control unit 2. FIG. 3 shows a timing diagram of the operation of control unit 2 for the case of five channels - of which the first and fourth channels are to be polled (the numbering of the channels starts from zero). The division factor of the 18K divider should be no less than the total number of polled channels S, since in the case of polling only one channel it is necessary before the arrival of the next pulse from the output of divider 18 to shift to the full cycle the contents of the register 1 9.

Claims (2)

1. A device for compressing and transmitting telemetry information containing a switch, whose information inputs are the first inputs of the device, the output of the switch is connected to the first inputs of the first comparison unit and the memory block through an analog-to-digital converter. the input of the first comparator unit, the second comparator unit, the output of which is connected to the first input of the reader unit, the output of which is the first output of the device, and a synchronizer, characterized in that, in order to increase the informativeness of the device, the control unit, counters, and elements are entered into it and the delay element, the synchronizer output is connected to the first input of the control unit, the second input of which is the second input of the device, the first output of the control unit is connected to the first input of the first counter, the second input of which It is connected to the third input of the control unit and is the third input of the device, the second output of the control unit and the output of the first counter are connected respectively to the first and second inputs of the first element And whose output is connected to the control input of the switch, the first inputs of the second counter and the second comparison unit the second inputs of the readout unit and the memory unit, the output. The first comparison unit is connected to the input of the delay element, the second input of the second counter, the third input of the memory unit and the first input of the second element And whose second input is connected to the output of the analog-digital converter, the output of the second element And is connected to the third input of the reader, the output and the third input of the second counter are connected respectively, with the second input and the output of the second comparison unit, the output of the delay element is the second output of the device. 2. The device according to claim 1, wherein the control unit is executed on a frequency divider, shift register, trigger, OR elements and AND elements, the output of the frequency divider and the output of the first element AND are connected respectively to the first and second inputs of the first element OR, the output of which is connected to the trigger input, the trigger output is connected to the first inputs of the first AND element and the second OR element, the output of which is connected to the first input of the second element AND, the output of which is connected to the second input of the first element AND and the first input of the shift register and is the first output of the control unit, the output of the shift register connected to its second input and second input the second element OR, the second and third inputs The second element And, the third register input and the output of the frequency divider are respectively the first, third and second inputs and the second output of the control unit. .: Synchronizer output Trampling Output divider G8 Exit Te rs Exit or JG J Exit and 17 1 bit d KG 19 J 2 bit d KG 19 Z ra r dYy19 J bit d KS 19 -f 5pa3pfldKGJ9 FIG. 2 Fig.Z j